Memory Cell String Matching via Complementary Threshold Pairs
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Solution Overview
Problem
The miniaturization of semiconductor memory has reduced the voltage range of bit lines, making them susceptible to noise and leak voltages, which complicates the accurate detection of arithmetic results.
Innovation Solution
The use of transistor pairs with complementary thresholds in a memory cell array, where each transistor stores complementary data, allows for the detection of matching elements by monitoring the voltage of the bit line, which decreases only when all elements match.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor memory is miniaturized to increase integration density, then storage capacity is improved, but voltage range of bit lines is reduced making them susceptible to noise and leak voltages
Solution Approach 1:
The patent introduces a bit line voltage storage unit as an intermediary component that captures and holds the bit line voltage state after arithmetic operations. This mediator allows the system to preserve the computational result even when the original bit line voltage becomes unreliable due to miniaturization effects, noise, or leakage, thereby maintaining detection accuracy without sacrificing integration density
Solution Approach 2:
The system performs beforehand cushioning by pre-storing the bit line voltage in the voltage storage unit immediately after the arithmetic operation completes. This preparatory action cushions against subsequent voltage degradation from leakage or noise, ensuring the stored voltage remains stable and detectable even as memory cells are miniaturized
2Volume of moving object
If voltage range of bit lines is reduced due to miniaturization, then integration density is improved, but accuracy of detecting arithmetic results deteriorates
Solution Approach 1:
The bit line voltage storage unit serves as an intermediary that decouples the detection process from the degraded voltage signal. By storing the voltage state in a dedicated unit with appropriate holding characteristics, the system maintains measurement precision even when the bit line voltage range is reduced due to smaller memory cell dimensions
Solution Approach 2:
The system creates a copy of the bit line voltage state by transferring it to the voltage storage unit. This copied voltage representation preserves the arithmetic result information in a stable form that is independent of the original bit line's vulnerable voltage state, enabling accurate detection despite miniaturization
3Productivity
If bit line voltage level is easily affected by noise and leak voltage, then system complexity increases, but arithmetic processing speed is improved
Solution Approach 1:
The voltage storage unit acts as a simple intermediary that captures the voltage state without requiring complex real-time noise filtering or stabilization circuits. This approach maintains high arithmetic processing speed while adding only minimal detection system complexity through a straightforward voltage holding mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables simple and quick detection of matching elements by ensuring a current flows only when all elements are matched, improving the accuracy and speed of arithmetic processing in semiconductor memory.
Implementation Method 1
a voltage signal based on second input data is applied to a word line, and a voltage level of a bit line connected to the memory cell is changed according to an arithmetic result
Data Source
AI summary
An information processing apparatus that detects whether the corresponding first element and second element among the multiple first elements and the plurality of second elements are matched or are similar, has one or multiple strings connected to a first wiring and connected to multiple second wirings, wherein the string includes multiple transistor pairs connected in series along a current path having one end connected to the first wiring, each of the multiple transistor pairs includes a first transistor and a second transistor connected in series along the current path, the second wirings are connected to gates of the first transistor and the second transistor in each of the multiple transistor pairs, the first transistor is set to a first threshold depending on first data, the second transistor is set to a second threshold depending on second data that is complement data of the first data.