Semiconductor Memory Device Program Voltage Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in ensuring uniform program speeds across memory cells, leading to widened threshold voltage distribution due to varying program voltage magnitudes and cell programming speeds.
Innovation Solution
A semiconductor memory device and operating method that adjust program permission voltages based on the arrangement positions of memory strings, applying negative potential levels to selected memory strings and program prohibition voltages to unselected ones, thereby controlling program speeds and improving threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single program voltage is applied to all memory strings, then the program operation is simple to control, but the program speeds of different memory cells become non-uniform leading to widened threshold voltage distribution
Solution Approach 1:
The patent applies different program permission voltage levels to different memory strings based on their arrangement positions. Specifically, memory strings at different locations receive different voltage levels (e.g., first program permission voltage for first memory strings, second program permission voltage for second memory strings) to compensate for position-dependent program speed variations, thereby achieving uniform threshold voltage distribution across all memory cells.
Solution Approach 2:
The patent changes the voltage parameter of program permission signals applied to bit lines based on the arrangement position of memory strings. By adjusting the voltage level parameter according to position, the patent compensates for variations in program speed and narrows the threshold voltage distribution width.
2Manufacturing precision
If program permission voltages are adjusted according to memory string positions, then uniform program speeds are achieved, but the voltage control complexity increases
Solution Approach 1:
The patent divides the memory cell array into multiple groups based on arrangement positions (e.g., first memory strings and second memory strings). Each group is assigned a specific program permission voltage level, allowing uniform program speeds to be achieved through segmented voltage control rather than individual cell control.
Solution Approach 2:
The control logic unit performs multiple functions: it determines arrangement positions of memory strings, selects appropriate program permission voltage levels, and generates control signals for bit lines. This multi-functionality reduces the need for separate control mechanisms for each memory string.
Data Source
AI summary
There may be provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array including a plurality of memory strings. The semiconductor memory device may include a peripheral circuit for performing a program operation on the plurality of memory strings, and a control logic for controlling the peripheral circuit to perform the program operation. The control logic may control the peripheral circuit to adjust potential levels of program permission voltages to be applied to the plurality of memory strings according to arrangement positions of the memory strings.