Memory String Write Sequencing for Disturb-Resistant Multi-Bit Storage
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Solution Overview
Problem
Current semiconductor storage devices face reliability issues due to disturbances during write operations, which can lead to incorrect data storage and reading failures, especially when multiple bits are written simultaneously.
Innovation Solution
A semiconductor storage device design that divides the write operation into two stages: a first write operation and a second write operation, where the first operation sets a coarse threshold voltage distribution, and the second operation refines it, minimizing the impact of disturbances from adjacent memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bits are written simultaneously to memory cells, then writing speed is improved, but disturbance to adjacent memory cells increases causing reliability degradation
Solution Approach 1:
The write operation is divided into two distinct stages: a first write operation that sets a coarse threshold voltage distribution, and a second write operation that refines the threshold voltage. This segmentation allows the system to maintain high productivity by performing bulk operations in the first stage while ensuring reliability through targeted refinement in the second stage, thereby resolving the contradiction between writing speed and data storage reliability.
Solution Approach 2:
The first write operation performs preliminary action by establishing a coarse threshold voltage distribution before the second write operation refines it. This preliminary action reduces disturbance to adjacent memory cells during the refinement phase, as the voltage adjustments are smaller and more targeted, thus improving reliability without sacrificing overall writing efficiency.
2Ease of operation
If a single write operation is used, then operation simplicity is maintained, but disturbance to adjacent memory cells causes reading failures
Solution Approach 1:
The write operation is segmented into two distinct phases: a first write operation establishing coarse threshold voltage levels and a second write operation refining those levels. This segmentation improves reading accuracy by reducing adjacent cell disturbance during the refinement phase, while the automated two-stage process maintains ease of operation through integrated control logic that manages both stages sequentially without requiring complex external intervention.
3Reliability
If coarse threshold voltage distribution is set first, then disturbance impact is minimized, but additional write operation increases time consumption
Solution Approach 1:
The write operation is divided into two stages where the first stage sets coarse threshold voltage distribution quickly with minimal disturbance, and the second stage performs targeted refinement. This segmentation optimizes the balance between reliability and time consumption by performing bulk operations efficiently in the first stage and applying minimal necessary adjustments in the second stage, reducing overall time loss compared to traditional single-stage operations.
Solution Approach 2:
The first write operation performs partial action by establishing only the coarse threshold voltage distribution without completing the full refinement process. This allows the system to achieve significant reliability improvement with reduced time consumption in the first stage, while the second stage completes the necessary refinement with minimal additional time investment, as it only addresses specific threshold adjustments rather than performing a complete write operation.
Data Source
AI summary
A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.