3D Memory Cell Strings With Conductor-Tier Coupling Integrity
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Solution Overview
Problem
Current memory array fabrication methods face challenges in efficiently forming strings of memory cells with precise electrical coupling and material composition, which affects the reliability and performance of memory arrays.
Innovation Solution
The method involves forming a conductor tier with laterally-spaced memory-block regions comprising alternating conductive and insulative tiers, where channel-material strings extend through these tiers, and conducting material is used to electrically couple the channel material with the conductor tier, with specific compositions of carbon, nitrogen, oxygen, metal, and n-type doped semiconductive materials to enhance etching protection and material differentiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory array fabrication methods are used, then manufacturing process is simpler, but electrical coupling reliability and material integrity deteriorate
Solution Approach 1:
The patent applies preliminary action by forming a conductor tier before forming the memory block regions, establishing a stable electrical foundation in advance. The conductor tier is formed with specific materials and structures that prepare the substrate for subsequent memory cell formation, ensuring reliable electrical coupling is established before other components are added.
Solution Approach 2:
The patent segments the memory array into distinct functional tiers: a conductor tier for electrical coupling, memory block regions with alternating conductive and insulative tiers, and channel-material strings. This segmentation allows each component to be optimized independently while ensuring proper electrical isolation and coupling between layers.
2Ease of manufacture
If material composition is simplified, then manufacturing is easier, but etching protection and material differentiation deteriorate
Solution Approach 1:
The patent employs composite materials by specifying multi-component material compositions for different tiers. The conductor tier uses conductive materials, while memory blocks alternate between conductive and insulative materials. Channel-material strings use semiconductive materials with specific doping configurations, creating distinct material signatures that enable precise differentiation during fabrication.
Solution Approach 2:
The patent applies local quality by assigning different material compositions to specific regions and tiers. Each memory block region has locally optimized material stacks with alternating conductive and insulative properties, while channel-material strings have locally controlled doping profiles. This local differentiation enables precise etching and processing while maintaining overall manufacturing feasibility.
3Productivity
If conductor tier structure is simplified, then fabrication is faster, but electrical coupling between channel material and conductor tier deteriorates
Solution Approach 1:
The patent transitions from planar electrical coupling to three-dimensional vertical coupling by forming a conductor tier that extends beneath and connects to multiple memory block regions. The conductor tier creates vertical electrical pathways through the alternating conductive and insulative tiers, enabling efficient charge transport in the vertical dimension while maintaining fabrication efficiency.
Solution Approach 2:
The conductor tier serves multiple functions simultaneously: it provides electrical coupling to channel-material strings, acts as a common reference potential for multiple memory blocks, and enables charge transport across the memory array. This multi-functionality achieves reliable electrical coupling without requiring separate structures for each function, maintaining fabrication productivity.
Data Source
AI summary
A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lowest of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. An uppermost portion of the conductor material comprises conductively-doped semiconductive material that is directly against the conducting material, of different composition from that of the conducting material, and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type conductively-doped semiconductive material also comprising boron. Other embodiments, including method, are disclosed.


