3D Memory Cell Strings With Dopant-Barrier Lower Gate Structure
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Solution Overview
Problem
Existing memory array fabrication methods face challenges in minimizing undesired etching of materials during the formation of memory cells, particularly in the transition from gate-last or replacement-gate processing, which can affect the integrity and performance of the memory cells.
Innovation Solution
A method involving the formation of a conductor tier with alternating insulative and conductive tiers, followed by the creation of channel openings and trenches, and the use of conductively-doped semiconductive material to electrically couple channel material with the conductor tier, while incorporating an intermediate material to prevent upward migration of conductivity-enhancing dopants, thereby stabilizing the memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate-last or replacement-gate processing is used to form memory cells, then manufacturing flexibility and device performance are improved, but undesired etching of materials occurs during the formation process
Solution Approach 1:
A sacrificial material layer is introduced as an intermediary component between the channel material and the gate electrode. This sacrificial layer serves as a protective barrier during etching operations, preventing undesired etching of the channel material while allowing the gate structure to be formed. After the gate is formed, the sacrificial material is removed, having fulfilled its protective function during the critical manufacturing stage.
Solution Approach 2:
The sacrificial material layer is deposited and patterned before the gate electrode formation process begins. This preliminary action establishes a protective framework in advance that will shield the channel material during subsequent etching operations, ensuring that the channel material remains intact throughout the gate formation process.
2Device complexity
If conventional fabrication methods are used, then manufacturing simplicity is maintained, but undesired etching affects the integrity and performance of memory cells
Solution Approach 1:
The sacrificial material acts as a temporary intermediary structure that protects the channel material from etching damage. This addition of a temporary protective layer significantly improves memory cell integrity during fabrication, while the layer is designed to be easily removed afterward, minimizing the added complexity to the overall fabrication process.
3Reliability
If dopants are introduced to enhance conductivity in memory cells, then electrical performance is improved, but dopant migration destabilizes the memory cell structure
Solution Approach 1:
The sacrificial material layer serves as a physical barrier that prevents dopant migration during thermal processing and fabrication steps. By blocking the movement of dopant atoms, this intermediary layer maintains dopant position stability and prevents compositional destabilization of the memory cell structure, while still allowing dopants to be introduced for enhancing electrical conductivity.
Solution Approach 2:
The sacrificial material layer is introduced in advance to counteract the potential harmful effect of dopant migration. This preliminary protective action prevents dopants from migrating to unwanted locations during subsequent processing steps, thereby maintaining the stability of the memory cell composition before any destabilization can occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes undesired etching and enhances the structural integrity of memory cells, ensuring reliable electrical coupling and performance by restricting dopant migration, thus improving the overall efficiency and reliability of the memory array.
Implementation Method 1
conductively-doped semiconductive material that directly electrically couples together the channel material
Implementation Method 2
intermediate material... comprising at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron
Data Source
AI summary
A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, are disclosed.