Memory Stripe Error Correction Using Enlarged RS Codewords
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Solution Overview
Problem
Existing Reed-Solomon (RS) error correction codes in memory devices are ineffective in correcting errors when more than one data die fails, leading to unreliable memory systems, unrecoverable data, and high power and storage consumption.
Innovation Solution
Implementing double device data correction (DDDC) by associating multiple memory stripes with each other, using enlarged RS codewords to correct errors in both stripes, allowing for recovery of data even after multiple die failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Reed-Solomon error correction codes are used in memory devices, then single die failures can be corrected, but multiple die failures result in unrecoverable data and system reliability degradation
Solution Approach 1:
The patent combines multiple memory stripes into a single enlarged Reed-Solomon codeword structure. Instead of treating each stripe independently with separate error correction codes, the invention merges data from multiple stripes (e.g., 4 stripes) into one unified codeword, allowing the error correction mechanism to operate across the entire merged structure. This enables correction of multiple die failures that would be uncorrectable in individual stripes.
Solution Approach 2:
The patent extends the error correction capability from a single-die dimension to a multi-die dimension by creating enlarged codewords that span multiple memory stripes. The Reed-Solomon code parameters are scaled up (e.g., from RS(512,256) to RS(2048,1024)) to provide correction capability across multiple dies, effectively adding a spatial dimension to the error protection scope.
2Loss of information
If error correction capability is enhanced to correct multiple die failures, then data recoverability improves, but power consumption and storage overhead increase
Solution Approach 1:
The enlarged Reed-Solomon codeword structure serves multiple functions simultaneously: it provides error correction for multiple die failures, maintains compatibility with existing memory architectures, and enables scalable protection across different numbers of stripes. The same codeword structure can protect 2, 4, or more stripes depending on configuration, providing universal error protection without requiring separate mechanisms for different failure scenarios.
3Reliability
If enlarged Reed-Solomon codewords are implemented across multiple memory stripes, then multiple die failures can be corrected, but device complexity increases
Solution Approach 1:
The patent segments the memory system into multiple stripes that are independently addressable and can be independently accessed, while the error correction operates on the merged codeword. This segmentation allows the memory controller to read only the affected stripes when errors occur, rather than processing entire memory arrays, thereby managing complexity through localized operations on segmented data portions.
Data Source
AI summary
In some implementations, a memory device may associate a first memory stripe with a second memory stripe. The memory device may receive a first codeword associated with the first memory stripe. The memory device may identify, using the first codeword, a first error in a first set of data bits that are associated with the first memory stripe. The memory device may correct the first error using the first codeword. The memory device may receive a second codeword associated with the first memory stripe and the second memory stripe. The memory device may identify, using the second codeword, a second error in a second set of data bits that are associated with the first memory stripe and the second memory stripe. The memory device may correct the second error using the second codeword.