Memory Striping Approach for Channel-Independent ECC Reconfiguration

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Solution Overview

Problem

The existing memory striping approach from a pair of 8+2 channels to a 16+2 configuration results in extended downtime due to a 'blast radius' affecting all memory chips, even when only one channel has a failing memory chip, as the striping pattern changes drastically, disrupting the information content across all channels.

Innovation Solution

The improved memory striping approach breaks down the pre-failure protected data word into two smaller protected sub-words with a higher ECC-to-data ratio, allowing for error correction if another memory chip fails, and re-stripes the data to confine the blast radius to the failing channel, maintaining operation with a smaller physical memory capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory striping pattern is changed from 8+2 to 16+2 configuration after a memory chip failure, then the system can continue operation with reduced memory capacity, but the downtime is extended due to the blast radius affecting all memory chips

Engineering Contradiction:

Improvesystem operation continuityVSAvoiddowntime

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the memory system into independent segments (channels) where each channel can be re-striped independently. When a failure occurs in one channel, only that channel undergoes re-striping while other channels continue operating with their original striping patterns, thus segmenting the blast radius and reducing overall downtime.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by allowing different channels to have different striping configurations simultaneously. The failed channel is re-striped to 16+2 configuration while successful channels maintain their 8+2 configuration, optimizing each channel's configuration based on its operational status rather than forcing a global re-configuration.

Inventive Principle:

Principle #3Local quality

2Adaptability or versatility

If the striping pattern is changed to accommodate a failed memory chip, then the system can operate with reduced physical memory, but the information content across all channels is disrupted

Engineering Contradiction:

Improvememory configuration adaptabilityVSAvoiddata access disruption

Core Design Contradiction:

Adaptability or versatilityVSLoss of information

Solution Approach 1:

The patent segments the memory address space by channel, allowing each channel to be re-striped independently. This prevents information loss in successful channels since their striping patterns remain unchanged, while the failed channel can be re-striped without affecting data accessibility in other channels.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory controller is designed to handle multiple striping configurations simultaneously across different channels, providing universal functionality that adapts to various failure scenarios while maintaining data integrity and access continuity across the entire memory system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12099408B2Memory striping approach that interleaves sub protected data words

Publication Date: 2024.09.24 INTEL CORP

AI summary

An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.