Memory System Striping for RAID Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current computer memory systems face bottlenecks in data access time due to the latency associated with persistent storage media, particularly in large data sets, where random access to memory locations is slow and the lifetime of FLASH memory devices is limited by wear-out mechanisms, leading to performance issues and increased complexity in managing data latency and error correction.
Innovation Solution
A memory system comprising a plurality of modules where only one module performs write or erase operations at a time, allowing for concurrent reading of user data from modules not engaged in write or erase operations, and utilizing error correcting codes to manage data integrity and reconstruct data in case of module failures, thereby minimizing latency and optimizing data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory modules are used for persistent storage, then storage capacity and data retention are improved, but data access latency increases due to sequential write/erase operations blocking read operations
Solution Approach 1:
The memory system is divided into multiple independently addressable modules, each capable of simultaneous read and write/erase operations. The controller segments data operations across modules, allowing parallel processing where reads can occur on modules not currently performing writes or erases, thereby reducing access latency while maintaining high storage capacity
Solution Approach 2:
The controller tracks the operational state of each memory module in advance and directs read requests to modules that are not currently engaged in write or erase operations. This preliminary state monitoring and intelligent routing prevents read operations from being blocked by ongoing write/erase operations on the same modules
2Reliability
If error correction mechanisms are implemented in persistent storage, then data reliability is improved, but system complexity increases due to additional processing overhead
Solution Approach 1:
Error correction code storage and data storage are merged into the same memory module structure. ECC data is stored alongside user data in the same module, allowing the controller to retrieve both simultaneously in a single read operation, thereby providing error correction capability without significantly increasing system complexity or access latency
3Duration of action of stationary object
If FLASH memory wear-out mechanisms are addressed through redundant modules, then device lifespan is improved, but data access performance deteriorates due to wear leveling overhead
Solution Approach 1:
The controller automatically manages wear leveling by tracking erase counts and operational states of each module, redistributing write and erase operations across modules to equalize wear. This self-managed wear leveling occurs in the background without requiring intervention that would slow down data access operations, thereby extending device lifespan while maintaining performance
Data Source
AI summary
A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.