Memory Controller Striping for Consistent SSD Write Throughput
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Solution Overview
Problem
The inconsistency in write throughput of non-volatile memory devices, such as SSDs, due to varying program times of word-lines in memory blocks, leads to reduced stability and performance during data write operations.
Innovation Solution
A memory controller that assigns different indices to sub-blocks within memory blocks based on characteristic parameters, allowing parallel data writing across these sub-blocks to construct a super-block, thereby ensuring uniform write throughput without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written to memory blocks in parallel with varying program times, then write throughput increases, but write throughput consistency deteriorates
Solution Approach 1:
The memory block is divided into multiple sub-blocks, and the write operation is segmented into multiple stripes. Each stripe contains data for one sub-block from each memory block in the super-block. This segmentation allows the write operation to be distributed across multiple parallel channels while maintaining consistency within each stripe, resolving the contradiction between parallel write throughput and throughput consistency.
Solution Approach 2:
Before executing the parallel write operation, the memory controller performs preliminary actions including: (1) dividing the memory block into sub-blocks and assigning indices, (2) constructing the super-block by selecting one sub-block from each memory block, (3) dividing data into stripes according to the sub-block indices. These preliminary organizing actions ensure that when parallel writing occurs, the varying program times of different word-lines do not cause throughput inconsistency.
2Productivity
If sub-blocks are introduced to enable parallel writing, then write performance improves, but system complexity increases
Solution Approach 1:
The introduced components (indexer, super-block constructor, stripifier) are integrated into the existing memory controller architecture. The indexer assigns indices to sub-blocks, the super-block constructor assembles super-blocks from sub-blocks, and the stripifier divides data into stripes. These multi-functional components handle both the organization of sub-blocks and the execution of parallel writes, improving write performance while minimizing the increase in system complexity through unified control.
Data Source
AI summary
A memory controller comprises a processing circuit configured to control a non-volatile memory to write data to sub-blocks included in a first super-block in a parallel manner to each other, in response to a first write command from a host, an indexer configured to assign respectively different indices from 1 to n to sub-blocks included in each of a plurality of memory blocks of the non-volatile memory based on a characteristic parameter, in response to a stripe request from the processing circuit, in which n is a natural number greater than or equal to 2, and a super-block constructor configured to select one sub-block from each of the plurality of memory blocks and assemble a first selected sub-blocks so that the first selected sub-blocks have at least indices from 1 to n.