Multi-Rank Memory Interface Circuit for Data Strobe Alignment

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Solution Overview

Problem

High-performance memory systems for information devices require efficient data strobe alignment and sampling to manage varying timing deviations among multiple data signals, which existing technologies struggle to address effectively, especially in multi-rank memory systems.

Innovation Solution

An electronic circuit comprising a delay line circuit and a sampling circuit that generate and align data strobes with data signals, ensuring proper sampling across multiple ranks by adjusting timing deviations, and a merge circuit that splits and delays data strobes to align with specific logical values of data signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple data signals are transmitted through a single channel in a multi-rank memory system, then the total capacity of the memory system increases, but timing alignment becomes more complex and difficult to manage

Engineering Contradiction:
Improvememory capacityVSAvoidtiming alignment complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the single data strobe signal into multiple separate data strobe signals (first data strobe, second data strobe, etc.), each dedicated to a specific data signal. This segmentation allows independent timing control for each data-strobe pair, simplifying the timing alignment process while maintaining the ability to transmit multiple data signals through the same physical channel.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces delay line circuits that pre-adjust the timing of data strobe signals before they reach the sampling circuits. By performing timing alignment in advance through controlled delay, the system ensures proper synchronization is established before sampling occurs, making the overall timing management more predictable and less complex.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If data strobe timing is adjusted to align with data signals having different timing deviations, then sampling accuracy improves, but the circuit area required for delay lines and sampling increases

Engineering Contradiction:
Improvesampling accuracyVSAvoidinterface circuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent implements separate delay line circuits for each data strobe signal, allowing customized timing adjustments tailored to the specific timing deviation of each corresponding data signal. This localized timing control optimizes sampling accuracy for each signal pair without requiring excessive delay range in a single shared circuit, thereby reducing the overall circuit area.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies timing adjustment only to the extent necessary for each specific data signal's timing deviation, rather than using a single large delay range that would cover all possible deviations. This partial action approach minimizes the delay line circuit area while achieving sufficient sampling accuracy for each individual signal.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If separate delay line circuits are used for each data strobe signal, then timing alignment precision improves, but the number of circuits and overall complexity increases

Engineering Contradiction:
Improvetiming alignment precisionVSAvoidnumber of circuits
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the timing control function into separate delay line circuits, each handling one data strobe signal. This segmentation achieves high timing alignment precision for each signal independently. The complexity is managed by organizing these separate circuits in a systematic manner where each circuit is dedicated to a specific data-strobe pair, making the overall system more manageable than a single complex timing control unit.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10586575B2Interface circuit for multi rank memory
Publication Date: 2020.03.10 SAMSUNG ELECTRONICS CO LTD
  • US10586575B2 patent drawing
  • US10586575B2 patent drawing
  • US10586575B2 patent drawing

AI summary

An electronic circuit including: a first delay line circuit to generate a first data strobe by delaying a second data strobe, such that an edge of the first data strobe is aligned within a first time interval; and a sampling circuit to sample the first data signal at the edge of the first data strobe, wherein plural data signals include the first data signal and a second data signal, wherein timings of the plural data signals deviate from a reference timing of a reference data strobe by plural time lengths, wherein the first data signal deviates from the reference timing by a first time length of the plural time lengths, and wherein an edge of the second data strobe is aligned within a second time interval, wherein a timing of the second data signal deviates from the reference timing by a shortest time length of the plural time lengths.