On-Die Delay Range Calibration for Memory Strobe Signal Synchronization

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Solution Overview

Problem

The existing methods for calibrating the data access time of a strobe signal in memory devices are time-consuming, leading to decreased data throughput due to the need for sequential calibration across multiple clock cycles.

Innovation Solution

A circuit that includes a difference signal generator and a delay circuit to determine and adjust the external clock signal based on the time difference between the strobe signal and the external clock signal, allowing for adaptive modification of the strobe signal to be synchronous with the modified external clock signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If sequential calibration of DQS strobe is performed for multiple RE clock cycles, then the data access time tDQSRE can be calibrated within the required range, but the calibration time is extended and data throughput is decreased

Engineering Contradiction:
Improvedata access time calibration accuracyVSAvoiddata throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent performs delay calibration in advance during a calibration mode before normal data operations. The calibration circuit determines the optimal delay value by comparing the RE clock signal and DQS strobe signal, then stores this calibration value in a calibration register. This preliminary calibration action ensures that subsequent data operations can proceed without repeated calibration delays, thus resolving the contradiction between calibration accuracy and data throughput.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If delay is sequentially increased for multiple RE clock cycles to calibrate DQS strobe, then the data access time can be adjusted to within the tDQSRE range, but the calibration process takes extended time

Engineering Contradiction:
Improvedata access time adjustment precisionVSAvoidcalibration time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent changes the calibration approach from sequential incremental delay adjustment to direct delay value determination. The calibration circuit directly measures the time difference between RE clock and DQS strobe signals and calculates the required delay value in a single operation. This parameter change from iterative adjustment to direct calculation significantly reduces calibration time while maintaining the precision of data access time adjustment within the tDQSRE range.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10204668B1On die delay range calibration
Publication Date: 2019.02.12 SANDISK TECHNOLOGIES LLC
  • US10204668B1 patent drawing
  • US10204668B1 patent drawing
  • US10204668B1 patent drawing

AI summary

Disclosed is a system including a memory timing calibration circuit to calibrate a strobe signal of a memory device and a method of calibrating the strobe signal. The memory timing calibration circuit includes a difference signal generator coupled to a strobe signal generator and an external control circuit. The difference signal generator is configured to generate a difference signal indicating a time difference between the strobe signal from the strobe signal generator and an external clock signal from the external control circuit. The memory timing calibration circuit further includes a delay circuit coupled to the difference signal generator and the external control circuit. The delay circuit is configured to generate a modified external clock signal by delaying the external clock signal by a delay determined based at least in part on the difference signal.