Semiconductor Memory Data Strobe Delay Logic for Ring Back Prevention
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Solution Overview
Problem
Conventional semiconductor memory apparatuses experience reduced data storage speed, area inefficiency, and increased power consumption due to the need for delay logic to prevent ring back phenomena during data strobe signal toggling, which can cause data errors.
Innovation Solution
A semiconductor memory apparatus that generates multiple delayed data strobe signals and shifting CAS write latency signals to activate and deactivate the data strobe enable signal, allowing for data latching without delaying the data strobe signal, thereby preventing ring back phenomena and optimizing storage speed, area efficiency, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay logic is added to prevent ring back phenomena, then data errors are prevented, but data storage speed is reduced
Solution Approach 1:
The patent extracts the delay function from the critical data path by using a separate delay unit that operates on a different clock domain. The delay logic is taken out of the main data storage path and implemented as an independent module that generates delayed clock signals, thereby preventing ring back phenomena without blocking the main data flow and maintaining high storage speed.
Solution Approach 2:
The patent introduces an intermediary delay unit that acts as a mediator between the main clock domain and the data storage path. This intermediary component generates delayed clock signals to control the timing of data latching, preventing ring back phenomena through controlled timing adjustment rather than direct delay of the data signal itself, thus maintaining data storage speed.
2Reliability
If delay units are added to prevent ring back phenomena, then data errors are prevented, but area efficiency is reduced
Solution Approach 1:
The patent segments the delay function into a separate, dedicated delay unit that operates independently from the main data path. This segmentation allows the delay logic to be implemented in a compact, specialized module rather than distributing delay logic throughout the entire chip, thereby reducing the overall area occupation while maintaining the necessary timing control to prevent ring back phenomena.
Solution Approach 2:
The delay logic is extracted from the main data path and implemented as a separate unit, which reduces the area occupation in the critical data storage path. The extracted delay unit can be optimized independently and uses minimal resources to generate the necessary delayed clock signals, improving area efficiency while maintaining data accuracy.
3Reliability
If delay units are added to prevent ring back phenomena, then data errors are prevented, but power consumption is increased
Solution Approach 1:
The delay function is extracted into a separate unit that operates on a different clock domain, allowing the main data path to remain active without unnecessary delay operations. This extraction reduces power consumption by eliminating redundant delay logic from the critical path while maintaining the necessary timing control through the separate delay unit.
Solution Approach 2:
The delay unit operates periodically based on clock signals rather than continuously processing data through delay stages. This periodic operation mode reduces power consumption by activating delay functionality only when needed for timing control, rather than maintaining continuous delay operations that would consume excessive power.
Data Source
AI summary
A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data.