Memory Output Strobe Circuit for Synchronized DLL Edge Timing
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Solution Overview
Problem
Semiconductor memory devices face challenges in generating data output strobe signals with synchronized rising and falling edges, leading to clock skew and distorted data output due to differing rising and falling times of strobe signals, resulting in poor Vox characteristics and a small data valid window.
Innovation Solution
A semiconductor memory device with a data output strobe signal generation circuit that activates two clock signals with opposite phases at the same timing, using a delay locked loop to generate synchronized rising and falling DLL clock signals, and employing NAND gates to generate strobe signals that are phase-opposed and timed coincidentally, ensuring data output stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is used to generate data output strobe signals, then the circuit structure is simple, but clock skew occurs between rising and falling edges leading to distorted data output
Solution Approach 1:
The patent divides the single clock signal into two separate clock signals (rising DLL clock signal and falling DLL clock signal) that are generated independently through separate delay locked loop circuits. This segmentation allows each clock signal to be optimized for its specific edge timing, eliminating the clock skew that occurs when using a single clock signal for both rising and falling edges.
2Productivity
If rising and falling strobe signals are generated with different timings, then the circuit operation is simple, but the data valid window becomes small and Vox characteristics deteriorate
Solution Approach 1:
The patent employs delay locked loop circuits that use feedback mechanisms to automatically adjust and synchronize the timing of rising and falling DLL clock signals. The feedback ensures that both clock signals arrive at the strobe signal generation unit simultaneously, achieving precise timing synchronization without requiring complex manual adjustment circuits.
3Device complexity
If clock skew compensation is not implemented, then the device complexity is reduced, but clock skew between external and internal clock signals occurs
Solution Approach 1:
The patent introduces delay locked loop circuits as intermediary components between the external clock signal and the internal strobe signal generation. These intermediary circuits compensate for clock skew by adjusting the timing of internal clock signals to match the external clock signal, ensuring synchronized operation without adding excessive complexity to the overall system.
Data Source
AI summary
A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal.