Synchronous Memory Strobe Buffer for Glitch-Free Data Capture

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Solution Overview

Problem

Conventional buffer and control circuits for synchronous memory controllers are prone to data capture faults due to inaccurate representation of read operation stages, leading to potential glitches in the reference strobe signal, which can result in incorrect data transmission.

Innovation Solution

The proposed buffer and control circuit design includes differential comparators with pull-up and pull-down transistors and capacitors to prevent glitches in the reference strobe signal, ensuring accurate data capture by maintaining defined logic states and controlling voltage variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional buffer and control circuit design is used, then device complexity is reduced, but reliability deteriorates due to data capture faults and glitches in reference strobe signal

Engineering Contradiction:
Improvedata capture accuracyVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer and control circuit is divided into multiple functional segments: a first differential comparator for generating intermediate signals, a first pull-up transistor for voltage stabilization, a first control buffer circuit for signal conditioning, a second differential comparator for further signal processing, and a second pull-up transistor. Each segment performs a specific function to collectively ensure glitch-free reference strobe signal generation while maintaining manageable complexity through modular functional decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit performs preliminary actions by using pull-up transistors to pre-establish defined logic high states at critical intermediate points before signals are processed further. The first pull-up transistor pre-defines the logic state of the first intermediate signal, and the second pull-up transistor pre-defines the logic state of the second intermediate signal, preventing glitches before they can propagate to the reference strobe signal.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If differential comparators without pull-up transistors are used, then device complexity is reduced, but measurement precision deteriorates due to undefined logic states

Engineering Contradiction:
Improvelogic state definitionVSAvoidtransistor and capacitor addition
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Pull-up transistors are strategically placed at specific locations within the circuit where logic state definition is critical - specifically at the outputs of the differential comparators. This local application of the pull-up mechanism ensures that only the most critical signal transitions are stabilized, providing precise logic state definition where needed without adding complexity throughout the entire circuit.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The pull-up transistors change the voltage parameter of the intermediate signals by actively pulling them to defined logic high levels. This parameter change ensures that intermediate signals maintain stable, well-defined voltage levels throughout their propagation, preventing undefined states and improving the precision of subsequent signal comparisons and processing.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If voltage variations are not controlled, then device complexity is reduced, but reliability deteriorates due to glitches in reference strobe signal

Engineering Contradiction:
Improvereference strobe signal stabilityVSAvoidcontrol circuit elements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control buffer circuits provide feedback mechanisms that monitor and regulate the voltage levels of intermediate signals. The first control buffer circuit receives the first intermediate signal and conditions it before further processing, while the second control buffer circuit similarly processes the second intermediate signal. This feedback-based voltage regulation ensures stable reference strobe signal generation by correcting voltage variations before they can cause glitches.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8780649B2Buffer and control circuit for synchronous memory controller
Publication Date: 2014.07.15 NXP USA INC
  • US8780649B2 patent drawing
  • US8780649B2 patent drawing
  • US8780649B2 patent drawing

AI summary

A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.