High-Bandwidth Memory Write Strobe Phasing for Low-Power Transfer

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Solution Overview

Problem

High-speed data transmission in memory devices leads to increased power consumption due to high-frequency data strobe signals, which is not efficiently managed by existing technologies.

Innovation Solution

A memory device architecture that includes a buffer die and multiple core dies stacked through silicon through electrodes, with a write data strobe signal divider generating internal write data strobe signals with different phases, allowing for efficient data transmission and reduced power consumption by initializing these signals before the write data strobe signal toggles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transmitted at high speed using high-frequency data strobe signals, then data transmission speed is improved, but power consumption increases

Engineering Contradiction:
Improvedata transmission speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The memory device is divided into multiple independent channels, each with its own command/address receiver and control logic. This segmentation allows selective activation of channels based on data transmission needs, reducing overall power consumption while maintaining high-speed transmission capability on active channels

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control logic circuit generates a reset signal before the write data strobe signal starts to toggle, initializing the internal write data strobe signals to given values. This preliminary action ensures proper synchronization is established before high-speed data transmission begins, avoiding the need for continuous synchronization overhead during operation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11769547B2Memory device transmitting and receiving data at high speed and low power
Publication Date: 2023.09.26 SAMSUNG ELECTRONICS CO LTD
  • US11769547B2 patent drawing
  • US11769547B2 patent drawing
  • US11769547B2 patent drawing

AI summary

A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.