High-Bandwidth Memory Strobe Phasing for Lower Write Power
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Solution Overview
Problem
High-speed data transmission in memory devices leads to increased power consumption due to the use of high-frequency data strobe signals.
Innovation Solution
A memory device design with a buffer die and core dies stacked through silicon through electrodes, utilizing a write data strobe signal divider to generate internal strobe signals with different phases, reducing the need for separate synchronization and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency data strobe signals are used for high-speed data transmission, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The memory device is divided into multiple independent channels, each with its own data strobe signal. This segmentation allows selective activation of channels based on data transmission needs, reducing overall power consumption while maintaining high-speed transmission capability when needed.
Solution Approach 2:
Data strobe signals are activated periodically only during data transmission periods rather than continuously. The control logic circuit generates these periodic strobe signals synchronized with data latching requirements, eliminating unnecessary power consumption during idle periods while maintaining high-speed transmission when data is being transferred.
2Productivity
If multiple data strobe signals are used for multi-channel high-speed data transmission, then data transmission bandwidth is improved, but power consumption increases
Solution Approach 1:
The multi-channel interface is segmented into independent data transmission paths, each with dedicated control logic. This allows the system to activate only the necessary number of channels based on current data bandwidth requirements, achieving high productivity when needed while conserving power during lower-demand periods.
Solution Approach 2:
The control logic circuit is designed to universally manage multiple channels through a unified control mechanism. It can dynamically allocate data strobe signals across different channels based on demand, providing high bandwidth capability when multiple channels are active while reducing power consumption when fewer channels are needed.
3Reliability
If data strobe signals are continuously active for high-speed data transmission, then data integrity is improved, but power consumption increases
Solution Approach 1:
Data strobe signals are generated periodically only during data transmission intervals rather than continuously. The control logic circuit synchronizes these periodic signals with data latching operations, ensuring data integrity is maintained during transmission while power consumption is reduced during idle periods when continuous strobe signals are not needed.
Data Source
AI summary
A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.