Semiconductor Memory Bank Group Strobe Signal Pulse Width
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Solution Overview
Problem
Semiconductor memory devices face challenges in generating strobe signals with sufficient pulse width due to increased external clock cycle speeds, leading to operation errors and reduced data reading accuracy, especially when bank grouping modes are employed, which require extended CAS to CAS delays.
Innovation Solution
A semiconductor memory device design that allows multiple bank groups to share column address strobe pulse signals, generating strobe signals with expanded pulse widths using a control signal generating block and strobe signal generating units, enabling increased bank grouping without increasing the number of column address strobe pulse signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the external clock cycle is decreased to increase operating speed, then productivity is improved, but the pulse width of the strobe signal becomes too short to ensure proper voltage level difference generation
Solution Approach 1:
The patent applies preliminary action by extending the strobe signal pulse width beyond the minimum required duration. The strobe signal is generated with a pulse width that is deliberately made larger than the external clock cycle period, ensuring that sufficient time is available for generating the voltage level difference between main and sub local input/output lines even at high operating speeds. This preliminary extension of the signal duration prevents operation errors before they can occur.
Solution Approach 2:
The patent changes the temporal parameter of the strobe signal by extending its pulse width to be greater than the external clock cycle period. This parameter change ensures that the strobe signal maintains adequate duration for proper signal level generation while still operating at high clock speeds, thereby resolving the contradiction between operating speed and signal duration.
2Productivity
If bank grouping mode is used to control tCCD for high-speed operation, then productivity is improved, but the number of column address strobe pulse signals increases
Solution Approach 1:
The patent merges the generation of multiple strobe signals by using a single extended strobe signal that serves multiple bank groups. Instead of generating separate column address strobe pulse signals for each bank group, the invention uses one strobe signal with extended pulse width that can be shared across multiple bank groups, thereby reducing the total number of signals required while maintaining high-speed operation capability.
Solution Approach 2:
The extended strobe signal is designed to serve multiple functions simultaneously - it acts as the column address strobe for multiple different bank groups. This multi-functional approach allows a single signal to replace what would traditionally require multiple separate signals, reducing device complexity while preserving the ability to perform high-speed operations across all bank groups.
Data Source
AI summary
A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address.