Semiconductor Memory Device Data Strobe Timing Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in ensuring reliable data reading and writing operations due to variations in word line voltage rising speeds across different regions of the memory cell array, leading to inconsistencies in data strobe timing and reduced accuracy.
Innovation Solution
The semiconductor memory device employs a method where the timing of asserting the signal STB is adjusted based on the rising speed of the word line voltage, using delay circuits and D-F/F circuits to generate signals STB_NEAR, STB_MID, and STB_FAR, allowing for synchronized data strobing across different regions, thereby ensuring consistent data reading and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single data strobe timing is used for all memory cells, then the device complexity is reduced, but the reading accuracy deteriorates due to variations in word line voltage rising speeds across different regions
Solution Approach 1:
The memory cell array is divided into multiple regions (first region and second region) with different data strobe timings. The control circuit generates different data strobe signals (first data strobe signal and second data strobe signal) for different regions based on their respective word line voltage rising speeds, allowing each region to be read at its optimal timing
Solution Approach 2:
Different data strobe timings are applied to different regions of the memory cell array according to their local characteristics. The first region receives a first data strobe timing while the second region receives a second data strobe timing, optimizing reading accuracy for each region's specific word line voltage rising speed
2Measurement precision
If data strobe timing is adjusted for each region, then the reading accuracy is improved, but the device complexity increases due to multiple timing control circuits
Solution Approach 1:
The control circuit performs multiple functions: it generates both the first and second data strobe signals, manages different timing sequences for different regions, and coordinates with the word line voltage generation. This multi-functional approach avoids the need for separate dedicated timing control circuits for each region
3Measurement precision
If the word line voltage rising speed is increased, then the data strobe timing can be synchronized better, but the power consumption increases
Solution Approach 1:
The control circuit dynamically adjusts the data strobe timing based on the actual word line voltage rising speed. By detecting the rising speed and adjusting the timing accordingly, the system achieves synchronization without needing to continuously increase the word line voltage amplitude, thereby avoiding excessive power consumption
Data Source
AI summary
A semiconductor memory device includes first and second read modes, a first memory cell and a second memory cell; a first word line electrically connected to a gate of the first memory cell and a gate of the second memory cell; a first bit line electrically connected to the first memory cell; a second bit line electrically connected to the second memory cell; a first sense amplifier configured to determine data read from the first memory cell at a first timing in the first and second read modes; a second sense amplifier configured to determine data read from the second memory cell at a second timing different from the first timing in the first read mode; a second sense amplifier configured to determine data read from the second memory cell at a second timing different from the first timing in the first read mode; a delay circuit; and a controller.