Memory Sub-Bank Staggered Write Timing
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Solution Overview
Problem
As semiconductor processes shrink, timing parameters in memory devices increase, reducing semiconductor yield and necessitating a method to manage these parameters effectively.
Innovation Solution
The implementation of a memory device with multiple sub-banks that overlap and stagger write operations, hiding timing parameters such as write recovery time from the memory controller, allowing for efficient data write operations without affecting data processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If timing parameters are increased to accommodate smaller semiconductor processes, then manufacturing precision is improved, but productivity deteriorates due to reduced yield and increased write recovery time
Solution Approach 1:
The memory device is divided into multiple sub-banks (first sub-bank, second sub-bank) within each bank. This segmentation allows independent operation of sub-banks, enabling overlapping row cycles between different sub-banks while maintaining sufficient timing parameters within each sub-bank. The segmentation resolves the contradiction by providing timing margin at the sub-bank level while achieving higher overall productivity through parallel operations.
Solution Approach 2:
The patent implements staggered row cycle start times between sub-banks, where the start time difference is between 5% and 25% of the row cycle duration. This preliminary timing arrangement allows the first sub-bank to complete critical operations (word line enable, precharge) before the second sub-bank begins its cycle, ensuring sufficient timing margins are met while maximizing throughput through overlapping operations.
2Reliability
If write recovery time is increased to ensure reliable data writing, then reliability is improved, but loss of time increases, reducing manufacturing efficiency
Solution Approach 1:
The patent enables continuous data writing operations by overlapping row cycles between sub-banks. While the first sub-bank is performing write recovery operations, the second sub-bank simultaneously performs data write operations. This continuity eliminates idle time and ensures that write recovery reliability is maintained without sacrificing overall manufacturing throughput, as useful actions continue uninterrupted across the memory system.
Solution Approach 2:
The patent implements periodic staggering of row cycle start times between sub-banks, creating a rhythmic pattern where critical timing operations in one sub-bank are followed by data write operations in another sub-bank. This periodic action pattern ensures that write recovery time requirements are met periodically while maintaining continuous productivity through the alternating sequence of operations.
Data Source
AI summary
A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.