Memory Device Sub Bit Line Leakage Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile semiconductor memory devices, such as MRAM, face read failure due to varying voltage distributions in memory cells, which can be exacerbated by leakage currents and temperature changes, leading to reduced read margins and increased failure rates.
Innovation Solution
The implementation of a memory device configuration that includes a selected bit line, a reference bit line, and a sub bit line, along with a sense amplifier, which senses voltage differences between nodes to determine data, and control logic to manage leakage currents by selectively connecting sub bit lines to nodes, thereby adjusting the reference voltage to prevent read failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference cell is used to determine data stored in memory cells, then data reading capability is improved, but read failure occurs due to voltage distribution variations in memory cells
Solution Approach 1:
The patent creates a copy of the bit line configuration by introducing sub bit lines that replicate the leakage current paths of unselected memory cells. This copying approach allows the reference voltage to account for leakage effects without requiring complex corrections, thereby maintaining measurement precision while improving reliability
Solution Approach 2:
The patent adjusts the reference voltage parameter dynamically by connecting sub bit lines to the reference bit line through control logic. This parameter change compensates for voltage distribution variations caused by leakage currents and temperature changes, preventing read failure while maintaining data reading capability
2Quantity of substance
If the number of unselected memory cells increases, then memory array capacity is improved, but voltage distribution variation increases causing read failure
Solution Approach 1:
The patent segments the bit line system into selected bit lines, reference bit lines, and sub bit lines. This segmentation allows independent control and compensation for leakage currents from unselected memory cells, enabling larger memory arrays while maintaining voltage distribution stability
Solution Approach 2:
The sub bit lines act as intermediaries between the reference bit line and the memory cell array. They capture and transfer leakage current information to the reference voltage generation circuit, enabling compensation for voltage variations without directly modifying the main bit line structure
3Adaptability or versatility
If temperature changes occur, then environmental adaptability is improved, but leakage current increases causing read failure
Solution Approach 1:
The patent implements a feedback mechanism where sub bit lines continuously monitor leakage current effects on the reference voltage. The control logic adjusts the reference voltage based on this feedback, compensating for temperature-induced leakage variations and preventing read failure across different environmental conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents read failure by maintaining the sensing margin despite changes in voltage distribution and temperature, ensuring reliable data retrieval in nonvolatile memory devices.
Implementation Method 1
a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell
Implementation Method 2
The sub cell may include a magnetic tunnel junction element having a first end connected to the sub bit line
Data Source
AI summary
A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.