Memory Sub-System Sub-Block Allocation via Address Shifting
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Solution Overview
Problem
Memory devices face reliability issues due to varying read window budgets across wordlines, leading to bit errors and increased latency, particularly when scaling in the x-y direction, which affects system performance and quality of service.
Innovation Solution
A memory sub-system controller allocates sub-blocks by shifting physical addresses using predefined values to avoid high bit error rate clusters across dies, ensuring different wordlines are used for programming operations, thereby minimizing the use of sub-blocks with high read window budget degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices scale in the x-y direction to increase capacity, then storage density is improved, but read window budget degradation increases leading to higher bit error rates
Solution Approach 1:
The memory device is divided into multiple sub-blocks within each block, allowing the system to selectively access and operate on smaller segments rather than entire blocks. This segmentation enables the controller to avoid degraded sub-blocks while maintaining access to healthy portions of the memory, thus preserving reliability while scaling capacity.
Solution Approach 2:
Different sub-blocks within the same block are treated with different quality characteristics based on their individual read window budget status. The system identifies and avoids sub-blocks with high degradation while continuing to use sub-blocks with acceptable characteristics, applying local quality management rather than uniform treatment across entire blocks.
2Ease of operation
If conventional block allocation methods are used, then allocation simplicity is maintained, but programming operations frequently encounter high bit error rate clusters causing host timeouts
Solution Approach 1:
The system performs preliminary identification and classification of sub-blocks into different quality categories before programming operations occur. By pre-mapping sub-blocks to quality indicators and maintaining this information in metadata, the controller can quickly allocate operations to healthy sub-blocks without encountering high error rate clusters during actual programming, thus reducing host timeouts while maintaining operational simplicity.
3Device complexity
If entire blocks are used as allocation units, then allocation overhead is reduced, but inability to avoid degraded areas increases bit error rates
Solution Approach 1:
Blocks are segmented into multiple sub-blocks that can be independently allocated and managed. This allows the system to work with finer-grained units than entire blocks, enabling avoidance of degraded sub-blocks while maintaining reasonable allocation overhead through efficient metadata structures that track sub-block quality status.
Solution Approach 2:
The allocation system adds a new dimension of granularity by introducing sub-block level management between the traditional block and page levels. This intermediate dimension allows more flexible allocation decisions that can avoid degraded areas without requiring complex block-level management, thus reducing allocation overhead while improving reliability.
4Productivity
If sub-blocks with high read window budget degradation are used for programming, then allocation efficiency is improved, but bit error rates increase significantly
Solution Approach 1:
The system implements feedback mechanisms that continuously monitor and update the quality status of sub-blocks based on read window budget measurements. This feedback information is stored in metadata and used by the allocation algorithm to direct programming operations to healthy sub-blocks, ensuring both high allocation efficiency and low bit error rates by making informed allocation decisions rather than random or sequential assignment.
Data Source
AI summary
A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. The processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. The processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.