Non-Volatile Memory Sub-Block Control for Lower Circuit Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memories with sub-blocks require complex control circuits, leading to larger size and higher power consumption, complicating their operation and design.
Innovation Solution
Implementing a control circuit that allows only one sub-block per block to be open at a time, separating memory structure and peripheral circuitry onto separate dies for optimized manufacturing and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-volatile memory is divided into sub-blocks for independent operation, then operational efficiency and scalability are improved, but control circuit complexity increases
Solution Approach 1:
The memory block is divided into multiple sub-blocks that can be independently operated. Each sub-block can be individually opened, programmed, read, or erased without affecting other sub-blocks, enabling finer-grained control and improved operational efficiency through parallel processing capabilities.
Solution Approach 2:
The control circuit dynamically manages sub-block states by selectively opening only the required sub-block for operation while keeping others closed. This dynamic state management allows the system to adapt to different operational requirements and reduces the effective complexity by activating only necessary circuit portions.
2Adaptability or versatility
If control circuit is enhanced to manage multiple open sub-blocks, then memory functionality is improved, but power consumption increases
Solution Approach 1:
The control circuit implements dynamic sub-block management where only one sub-block is allowed to be in the 'open' state at any given time. This dynamic constraint reduces power consumption by minimizing the number of simultaneously active circuit paths while still providing full functionality when needed.
Solution Approach 2:
Sub-blocks are opened and closed in periodic sequences based on operational requirements. The system transitions between different sub-block states over time, ensuring that power-intensive operations are distributed across time rather than occurring simultaneously, thereby reducing peak power consumption.
3Ease of manufacture
If memory structure and peripheral circuitry are separated onto different dies, then manufacturing optimization is achieved, but device interconnection complexity increases
Solution Approach 1:
The memory device is segmented into separate functional components located on different dies: the memory structure (memory cells and sub-blocks) on one die and the peripheral circuitry (control logic and interface circuits) on another die. This segmentation enables independent optimization of each component for its specific manufacturing process while maintaining overall system functionality through controlled inter-die connections.
Data Source
AI summary
A non-volatile memory includes a plurality of non-volatile memory cells arranged in blocks. Each block includes multiple sub-blocks that can be independently erased and programmed. A control circuit is connected to the non-volatile memory cells. The control circuit is configured to independently erase and program sub-blocks of a same block. The control circuit is configured to only allow one sub-block per block to be open at a time.