Memory Sub-block Partitioning for Parallel Read-Modify-Write Operations
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Solution Overview
Problem
Increasing demand for memory bandwidth in network and switching devices, driven by higher port density and speeds, leads to limitations in read and write throughput, causing packet drops and performance bottlenecks.
Innovation Solution
Implementing a memory management technique that partitions memory into sub-blocks with associated parity blocks, allowing for simultaneous read and write operations across multiple dimensions, including parallel read-modify write operations, and using set-associative organization to manage conflicts and increase write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory bandwidth is increased to meet higher port density and speeds, then data access performance is improved, but device complexity increases
Solution Approach 1:
The memory is divided into multiple sub-blocks, each capable of independent access. This segmentation allows parallel read and write operations to occur simultaneously in different sub-blocks, increasing data access performance without requiring a complete redesign of the memory management system.
Solution Approach 2:
The patent introduces a new dimension of parallelism by enabling simultaneous read and write operations within the same memory block. This is achieved through specialized circuitry that allows read-modify-write operations to proceed in parallel with other memory accesses, effectively adding a temporal dimension to memory operations.
2Productivity
If port density and speeds are increased, then network throughput is improved, but memory write capabilities become insufficient leading to packet drops
Solution Approach 1:
The system performs preliminary actions by pre-fetching data and preparing write operations in advance. The read-modify-write capability allows the system to prepare modified data before the original read operation completes, ensuring that write operations can proceed without waiting for read operations to finish, thus preventing packet drops.
Solution Approach 2:
The patent ensures continuity of useful action by allowing read and write operations to overlap in time. The memory system maintains continuous data flow by enabling write operations to proceed while read operations are still in progress, eliminating idle time and ensuring uninterrupted network traffic handling.
3Speed
If memory read speed is increased to keep pace with port speeds, then lookup performance is improved, but write speed becomes the limiting factor
Solution Approach 1:
The patent merges read and write operations into a unified read-modify-write operation. By combining these operations and allowing them to proceed in parallel with independent memory accesses, the system achieves high read speeds while simultaneously maintaining write speed, as the write portion can execute without waiting for the read portion to complete.
Data Source
AI summary
Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read or write access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write access is increased by including a latency cache that stores data associated with a read command. Once a read-modify write command is received, the data stored in the data cache is used to update the parity block. In a memory without a parity block, write access is increased by adding one or more spare memory blocks to provide additional memory locations for performing write operations to the same memory block in parallel.