Memory Sub-Block Precharge Path Selection for Partial Erase
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Solution Overview
Problem
Current semiconductor memory devices with three-dimensional array structures face challenges in efficiently managing memory blocks and performing operations like partial erase operations, leading to issues with data reliability and operational efficiency.
Innovation Solution
The implementation of a memory device with sub-blocks that can be operated independently, using different precharge paths and program sequences based on the position of sub-blocks relative to string select lines and ground select lines, allowing for efficient partial erase operations and improved data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional array structure is used to increase memory capacity, then storage density is improved, but operational complexity and difficulty in managing memory blocks increases
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) with distinct positions relative to the common source line and bit lines. This segmentation allows independent operation of sub-blocks, simplifying the management of large memory capacities by breaking down complex block operations into manageable sub-block operations.
Solution Approach 2:
Different precharge paths are selected based on the specific position of the target sub-block within the memory block. Sub-blocks adjacent to the common source line use one precharge path, while other sub-blocks use alternative paths. This local adaptation optimizes operational efficiency for each region of the three-dimensional memory structure.
2Ease of operation
If conventional two-dimensional array structure is used, then operational simplicity is maintained, but memory capacity and storage density are limited
Solution Approach 1:
The patent transitions from a conventional two-dimensional array structure to a three-dimensional array structure with vertically stacked memory cells. This dimensional change dramatically increases storage density while maintaining operational simplicity through the sub-block segmentation strategy, where each sub-block can be independently accessed and operated.
3Reliability
If partial erase operation is implemented in sub-block units, then data reliability is improved, but device complexity increases
Solution Approach 1:
The memory block is segmented into multiple sub-blocks that can be independently erased. This allows partial erase operations to be performed on only the necessary sub-blocks containing data to be erased, improving data reliability by enabling selective erasure while reducing overall device complexity compared to erasing entire memory blocks.
Solution Approach 2:
Different precharge paths are selected based on the position of sub-blocks within the memory block. Sub-blocks adjacent to the common source line use a first precharge path, while other sub-blocks use a second precharge path. This localized approach optimizes the erase operation for each sub-block's specific position, enhancing data reliability while managing device complexity.
4Productivity
If different precharge paths are used based on sub-block position, then operational efficiency is improved, but control complexity increases
Solution Approach 1:
The control system selects different precharge paths based on the local position of each sub-block within the memory block. Sub-blocks adjacent to the common source line are precharged through a first path, while other sub-blocks use a second path. This localized control strategy improves operational efficiency by optimizing precharge operations for each region while keeping control complexity manageable through clear positional criteria.
Data Source
AI summary
A memory device may include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block may include first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device mat be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.