Memory Device Sub-Block Replacement Data Architecture
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Solution Overview
Problem
Next-generation memory devices face challenges with error frequency and stability, requiring improved methods to repair failures without compromising performance.
Innovation Solution
A memory device architecture that includes a main block and a sub-block, where the sub-block stores replacement data for faulty pages, allowing for data recovery without performance degradation, using a multi-bit address to access and replace data in both blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a main block with multiple first pages is used to store data, then storage capacity is improved, but error frequency increases due to larger block size
Solution Approach 1:
The memory device is divided into a main block containing first pages and a sub-block containing second pages. The multi-bit address is segmented into a first address for accessing first pages and a second address for accessing second pages. This segmentation allows the system to maintain large storage capacity in the main block while providing error correction capabilities through the separate sub-block structure.
2Reliability
If replacement data is stored in the sub-block to repair failures, then reliability is improved, but device complexity increases
Solution Approach 1:
The replacement data functionality is extracted into a separate sub-block that is distinct from the main data storage block. This sub-block contains second pages that store replacement data corresponding to first pages in the main block. By extracting the error correction function into a separate structure, the main block remains simple while gaining reliability through the dedicated replacement mechanism.
Solution Approach 2:
The sub-block with second pages serves multiple functions: it stores replacement data for faulty first pages, maintains correspondence through tag matching, and provides error correction without requiring separate correction circuits. This multi-functional design improves reliability while minimizing additional complexity.
3Speed
If a multi-bit address system is used to access first pages, then access speed is improved, but difficulty in detecting and measuring errors increases
Solution Approach 1:
The second address acts as an intermediary that selectively accesses second pages in the sub-block based on the multi-bit address from the first address. This intermediary addressing mechanism enables the system to quickly identify whether replacement data is needed without complicating the primary fast access path through the first address system.
Data Source
AI summary
A memory device includes: a main block that includes a plurality of first pages that are accessible based on a multi-bit address; and a sub-block that includes a plurality of second pages that are accessible based on a portion of bits of the multi-bit address, and stores a replacement data for replacing entire or a portion of the data of an accessed first page among the plurality of the first pages in a second page that stores the same tags as the other bits of the multi-bit address among the accessed second pages.