3D Memory Sub-Block Segmentation for NAND Flash Management
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Solution Overview
Problem
In 3-dimensional non-volatile memory systems, existing memory block management is inefficient due to large memory block sizes, leading to inefficient garbage collection, amplified write operation performance, and high current consumption during erase operations, particularly in NAND flash memory systems.
Innovation Solution
The method involves identifying and biasing bit lines to specific voltages using bit line biasing transistors, logically grouping memory addresses, and defining sub-memory blocks within the 3-dimensional memory array to reduce memory block size, allowing for faster garbage collection, reduced write operation amplification, and decreased current requirements during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory block size is kept large for scaling, then storage capacity increases, but garbage collection efficiency deteriorates and write operation amplification increases
Solution Approach 1:
The patent divides a large memory block into multiple sub-blocks, each associated with separate bit line groups. This segmentation allows independent management and operation of smaller sub-blocks, improving garbage collection efficiency while maintaining the overall large block structure for high storage capacity.
2Quantity of substance
If memory block size is kept large for scaling, then storage capacity increases, but write operation amplification increases
Solution Approach 1:
By segmenting the memory block into sub-blocks that can be independently operated via separate bit line groups, the system reduces write operation amplification. Only the necessary sub-blocks need to be programmed or erased, rather than entire large blocks, thus reducing redundant write operations and energy loss.
3Quantity of substance
If memory block size is kept large for scaling, then storage capacity increases, but current consumption during erase operations increases
Solution Approach 1:
The segmentation of memory blocks into sub-blocks with independent bit line groups enables selective erasure operations. Only the specific sub-blocks requiring erasure are targeted, significantly reducing the current consumption compared to erasing entire large blocks, while preserving the high storage capacity benefit of large block scaling.
4Productivity
If bit line groups are separated for sub-block definition, then memory management efficiency improves, but device complexity increases
Solution Approach 1:
The patent employs universal bit line biasing transistors that can selectively connect different bit line groups to different voltages. These transistors serve multiple functions: defining sub-block boundaries, enabling selective operations, and maintaining overall block integrity. This multi-functionality improves memory management efficiency without proportionally increasing device complexity.
Data Source
AI summary
A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.