Memory Sub-Channels for High-Density PCB Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems are limited to having at most three memory components daisy chained together on a single memory channel due to signal degradation and physical limitations of Printed Circuit Board (PCB) design, making it difficult to support more than three memory components effectively.
Innovation Solution
Dividing a memory channel into two or more memory sub-channels, each with two or more memory components connected via transmission lines and individually accessible, allowing for more than three memory components to be supported on a single channel by using additional data signal lines and a sub-channel routing mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory components are daisy chained on a single memory channel, then data transfer capability is improved, but signal degradation occurs and physical limitations are reached
Solution Approach 1:
The patent divides a single memory channel into multiple sub-channels (e.g., first sub-channel and second sub-channel), each capable of independently addressing and transferring data to different memory components. This segmentation allows the system to support more than three memory components by distributing them across multiple sub-channels, thereby maintaining signal integrity while enhancing overall data transfer capability.
2Quantity of substance
If more than three memory components are supported on a single channel, then memory capacity is improved, but device complexity increases due to additional routing requirements
Solution Approach 1:
By segmenting the memory channel into multiple sub-channels, the patent enables support for more memory components without proportionally increasing routing complexity. Each sub-channel has its own dedicated data signal lines and addressing mechanism, allowing memory components to be organized in a structured manner that scales more efficiently than a single-channel daisy-chain approach.
Solution Approach 2:
The patent introduces an additional dimension to the memory channel architecture by creating multiple sub-channels within a single channel. This dimensional expansion allows the system to address more memory components by adding sub-channel identifiers to the addressing scheme, rather than simply extending the single-channel daisy-chain which would linearly increase complexity.
Data Source
AI summary
A memory channel can be divided into two or more memory sub-channels, wherein each one of the memory sub-channels includes two or more memory components configured to store data made accessible on that memory sub-channel, and wherein the two or more memory components in each one of the memory sub-channels are respectively connected via at least one transmission line and can be individually accessed (addressed) on their associated sub-channel.