Nonvolatile Memory Sub Common Sources for Block Segmentation
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Solution Overview
Problem
The existing semiconductor nonvolatile memory devices face challenges in increasing the degree of integration and improving memory efficiency, particularly in the erase operation of memory blocks, where increasing the number of memory cells leads to increased word lines and pass transistors, resulting in larger row decoders and reduced wiring line patterning margins, and longer erase times.
Innovation Solution
The solution involves dividing each memory block into at least two sub-blocks, allowing for independent erase operations, which improves memory efficiency by enabling quick and efficient erasure of data in smaller capacities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to improve degree of integration, then the memory capacity is improved, but the number of word lines and pass transistors increases, resulting in larger row decoders and reduced wiring line patterning margins
Solution Approach 1:
The memory block is divided into multiple sub-blocks, each with its own dedicated sub common source. This segmentation allows the row decoder to operate on smaller subsets of memory cells simultaneously, reducing the complexity and area required for the row decoder while maintaining high memory capacity through parallel operation of multiple sub-blocks.
2Quantity of substance
If the number of memory cells is increased to improve degree of integration, then the memory capacity is improved, but the wiring line patterning margins are reduced
Solution Approach 1:
By dividing the memory block into sub-blocks with dedicated sub common sources, the wiring density in any given region is reduced. This segmentation creates more manageable wiring patterns with adequate spacing, improving manufacturability and reducing patterning errors while achieving high overall memory capacity through the combined sub-blocks.
3Reliability
If the erase operation is performed on the entire memory block, then the complete data erasure is achieved, but the erase time is increased
Solution Approach 1:
The memory block is divided into multiple sub-blocks that can be erased independently and simultaneously. This allows the erase operation to be parallelized across sub-blocks, significantly reducing the total erase time while ensuring complete data erasure by targeting all sub-blocks systematically.
Solution Approach 2:
Instead of erasing the entire memory block at once, the erase operation is applied to individual sub-blocks or selected sub-blocks based on needs. This partial action approach reduces erase time for operations that don't require full block erasure, while still achieving complete erasure when all sub-blocks are processed.
Data Source
AI summary
A nonvolatile memory device includes a memory block including a plurality of cell strings each of which includes memory cells electrically coupled with word lines stacked over a substrate; a plurality of sub common sources electrically coupled to one ends of the cell strings; and a plurality of bit lines electrically coupled to the other ends of the cell strings, wherein the memory block includes sub blocks respectively corresponding to the sub common sources, and cell strings electrically coupled to the same bit line among the cell strings are included in the same sub block.