Non-volatile Memory Cell Sub-control Line Segmentation
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Solution Overview
Problem
In non-volatile semiconductor memory devices, the repeated application of charge storage memory gate voltage to unprogrammed memory cells leads to unwanted charge storage, causing threshold voltage changes and disturbance, especially in densely packed configurations where multiple memory cells share the same word line, and there is a need for downsizing while minimizing disturbance.
Innovation Solution
The introduction of a non-volatile semiconductor memory device with a configuration that includes a first control line, intersecting second control lines, and switching mechanisms at their intersections, where sub-control lines act as gates for memory cells, allowing selective application of memory gate voltage to programmed cells while blocking it for unprogrammed cells, thereby reducing disturbance and enabling downsizing by sharing wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory cells are arranged densely along the EEPROM word line to achieve downsizing, then the device size is reduced, but disturbance occurs in unprogrammed memory cells due to repeated application of charge storage memory gate voltage
Solution Approach 1:
The patent divides the memory array into multiple blocks along the row direction, with each block having its own independent charge storage memory gate line. This segmentation allows selective application of charge storage memory gate voltage to only those blocks containing programmed memory cells, preventing disturbance in unprogrammed memory cells while maintaining dense overall arrangement for downsizing.
Solution Approach 2:
The patent applies different voltage conditions to different regions (blocks) of the memory array. Blocks containing programmed memory cells receive charge storage memory gate voltage for data readout, while blocks with unprogrammed memory cells do not receive this voltage, thereby applying local quality control to prevent disturbance only where necessary.
2Ease of operation
If charge storage memory gate voltage is applied to read data from programmed memory cells, then data readout is achieved, but unwanted charge is stored in unprogrammed memory cells causing threshold voltage change
Solution Approach 1:
By segmenting the memory into blocks with independent charge storage memory gate lines, the patent enables selective voltage application. Only blocks with programmed memory cells have their charge storage memory gate lines activated for data readout, while blocks with unprogrammed cells remain inactive, preventing the harmful effect of unwanted charge storage.
Solution Approach 2:
The patent introduces block selection circuitry as an intermediary that determines whether to apply charge storage memory gate voltage to each block based on the presence of programmed memory cells. This intermediary prevents direct application of voltage to unprogrammed cells while enabling readout from programmed cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the occurrence of disturbance in unprogrammed memory cells and achieves downsizing by allowing the sub-control lines and gates to be in a single wiring layer, improving the reliability and compactness of the memory device.
Implementation Method 1
voltage application from the first control line or the second control line to the other sub control lines provided with the memory cells into which data is not programmed is blocked by the switching mechanisms corresponding to the other sub control lines
Data Source
AI summary
A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.