Semiconductor Memory Device Sub-Matrix Bit Line Segmentation
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Solution Overview
Problem
Semiconductor memory devices with open bit line structures have low noise tolerance and larger chip sizes due to inefficient area usage, particularly requiring a dummy matrix that occupies significant space.
Innovation Solution
The semiconductor memory device is modified with sub-memory-cell areas and additional bit lines that form data transfer paths, utilizing shared sensing and amplifying units and load units to reduce chip size and area occupancy, eliminating the need for a dummy matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If an open bit line structure is used, then chip size is reduced, but noise tolerance deteriorates
Solution Approach 1:
The memory cell matrix is divided into first and second sub-memory-cell areas with different bit line configurations. The first sub-memory-cell area uses folded bit lines (first bit line and first bit line bar) while the second sub-memory-cell area uses open bit lines (second bit line and second bit line bar). This segmentation allows different regions to serve different functions: the folded bit line region provides noise reference signals, while the open bit line region reduces overall chip area.
Solution Approach 2:
The sensing and amplifying units serve multiple functions by handling both folded bit line signals (for noise reference) and open bit line signals (for data transfer). The same sensing and amplifying units process signals from both bit line configurations, eliminating the need for separate dedicated units for each bit line type.
2Reliability
If a folded bit line structure is used, then noise tolerance is improved, but chip size increases
Solution Approach 1:
The memory cell matrix is divided into first and second sub-memory-cell areas with different bit line configurations. The first sub-memory-cell area uses folded bit lines (first bit line and first bit line bar) while the second sub-memory-cell area uses open bit lines (second bit line and second bit line bar). This segmentation allows different regions to serve different functions: the folded bit line region provides noise reference signals, while the open bit line region reduces overall chip area.
Solution Approach 2:
The folded bit line structure (first bit line and first bit line bar) and open bit line structure (second bit line and second bit line bar) are merged into a single memory cell matrix. Both structures share the same sensing and amplifying units, combining the noise tolerance benefits of folded bit lines with the area efficiency of open bit lines.
3Reliability
If a dummy matrix is added to provide reference bit lines, then noise tolerance is improved, but area efficiency deteriorates
Solution Approach 1:
The reference bit line function is extracted from a separate dummy matrix structure and integrated directly into the memory cell matrix through the folded bit line configuration. The first bit line bar serves as the reference bit line within the same matrix area, eliminating the need for a dedicated dummy matrix and improving area efficiency while maintaining noise tolerance.
Data Source
AI summary
A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.