3D Memory Sub-Plug Segmentation for Parallel Programming
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Solution Overview
Problem
Current memory devices face challenges in increasing integration density and operating speed, particularly in programming and reading multi-bit data, which leads to increased program pulses and time due to the complexity of threshold voltage distributions.
Innovation Solution
The memory device employs a three-dimensional structure with first and second sub-plugs separated by a channel isolation pattern, allowing for separate programming and reading of data groups across multiple drain select lines, reducing the time required for programming and reading operations by dividing data into smaller groups and utilizing a triple-level cell method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data programming is performed in conventional memory devices, then data capacity increases, but programming time and operating speed deteriorate due to increased program pulses and complexity of threshold voltage distributions
Solution Approach 1:
The memory device divides main plugs into first and second sub-plugs, and divides page data into first and second data groups. Each data group is programmed into respective sub-plugs through separate programming operations, allowing parallel processing that reduces total programming time while maintaining multi-bit data capacity
Solution Approach 2:
The patent introduces a vertical three-dimensional structure with sub-plugs arranged in the vertical direction and connected to different select lines. This spatial arrangement allows simultaneous access to different data groups through different select lines, enabling parallel programming operations that reduce time loss
2Quantity of substance
If integration density is increased in conventional memory devices, then storage capacity improves, but operating speed deteriorates due to increased complexity in programming and reading operations
Solution Approach 1:
By segmenting main plugs into sub-plugs with separate select line control, the device can independently access and operate on different data groups. This segmentation maintains high integration density while enabling faster parallel operations that improve operating speed
Solution Approach 2:
The patent implements dynamic control through multiple select lines that can be independently activated. This allows flexible and rapid switching between different sub-plugs and data groups, enhancing operating speed while maintaining high integration density through efficient resource utilization
3Productivity
If page data is divided into multiple data groups for parallel programming, then programming speed improves, but device complexity increases due to multiple select lines and sub-plug structures
Solution Approach 1:
The division of main plugs into sub-plugs and page data into data groups creates a systematic parallel architecture. While this increases structural complexity, it enables significant productivity gains through parallel programming operations that can be performed simultaneously on different sub-plugs
4Loss of time
If triple-level cell method is used with sub-plug structure, then time for programming and reading operations is reduced, but manufacturing complexity increases
Solution Approach 1:
The sub-plug structure divides the memory cell into separable units that can be independently programmed and read. This segmentation enables the triple-level cell method to operate more efficiently by allowing parallel processing of multiple data groups, reducing operation time despite increased manufacturing complexity
Data Source
AI summary
The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.