Memory Sub-System Bad Block Remapping for On-Chip Copyback
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Solution Overview
Problem
Conventional memory sub-systems face performance and quality of service (QoS) issues due to the need for off-chip copyback operations when dealing with bad blocks, which increases latency and reduces memory capacity as bad blocks are not usable for data storage.
Innovation Solution
The memory sub-system remaps bad blocks in block stripes to create block stripes free of bad blocks, allowing for on-chip copyback operations between SLC and QLC memory, thereby avoiding the use of off-chip copyback operations and maintaining performance and QoS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If off-chip copyback operations are used for bad blocks, then data can be moved from SLC to QLC memory, but latency increases and performance deteriorates
Solution Approach 1:
The patent extracts bad blocks from block stripes and isolates them in separate bad block regions, allowing good blocks to be processed through on-chip copyback operations while bad blocks are handled separately. This separation enables the majority of operations to avoid off-chip latency.
Solution Approach 2:
The patent introduces a remapping mechanism that acts as an intermediary between bad blocks and the copyback operation. By remapping bad blocks to alternative locations and updating address translation tables, the system can redirect operations away from defective blocks without requiring off-chip intervention for every access.
2Reliability
If off-chip copyback operations are performed, then data transfer between SLC and QLC memory is possible, but quality of service deteriorates
Solution Approach 1:
The patent performs preliminary identification and remapping of bad blocks before copyback operations begin. By pre-processing block stripe information and creating remapping tables in advance, the system ensures that during actual copyback operations, all address translations are already resolved, preventing QoS degradation.
Solution Approach 2:
The patent extracts problematic bad block handling from the main copyback operation flow, isolating it to separate processing paths. This allows the primary data transfer operation to proceed with high QoS while bad block management is handled independently without impacting overall service quality.
3Reliability
If bad blocks are excluded from data storage, then data integrity is maintained, but memory capacity is reduced
Solution Approach 1:
The patent discards bad blocks from the active block stripe pool but recovers their storage function by allocating separate bad block regions. These recovered regions can store data with updated address mappings, effectively converting defective blocks into usable storage capacity while maintaining data integrity through remapping.
Solution Approach 2:
The patent changes the status parameter of bad blocks from 'unusable' to 'remapped usable' by updating address translation tables and block stripe information. This parameter change allows the same physical blocks to be reused for storage after remapping, increasing effective capacity without compromising integrity.
4Productivity
If conventional block stripe management is used with bad blocks, then memory structure is simple, but performance and QoS deteriorate
Solution Approach 1:
The patent segments the memory block space into distinct regions: good block regions for active copyback operations and bad block regions for remapped storage. This segmentation creates clear boundaries and management zones, making the complex remapping process more tractable while enabling high performance in the good block regions.
Solution Approach 2:
The patent introduces remapping tables and block stripe information structures as intermediaries between the controller and physical blocks. These intermediary data structures manage the complexity of bad block handling centrally, allowing the rest of the memory system to operate with simple, straightforward block management.
Data Source
AI summary
Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.