Memory Sub-System Caching and Page Swapping for Storage Access

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Solution Overview

Problem

Current memory sub-systems face challenges in efficiently providing both memory and storage services over a physical connection, particularly in optimizing data storage and retrieval performance, especially when dealing with power failures and limited volatile memory capacity.

Innovation Solution

A memory sub-system configured to use a portion of its fast memory as cache memory, leveraging the Compute Express Link (CXL) protocol to offer cache-coherent memory access, allowing for optimized storage and memory services by allocating volatile memory for cache operations and non-volatile memory for storage, with features like page swapping and command queuing to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a memory sub-system provides both memory and storage services over a physical connection, then service versatility is improved, but device complexity increases

Engineering Contradiction:
Improveservice versatilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory sub-system is configured to provide both memory services and storage services over a single physical connection. The same interface and protocol can operate in different modes depending on the operation type, allowing one system to fulfill multiple functions without requiring separate dedicated connections for memory and storage operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically switches between memory service mode and storage service mode based on the operation being performed. The interface and protocol behavior are adjusted in real-time according to whether the operation is a memory access or a storage access, enabling flexible adaptation without permanent structural complexity.

Inventive Principle:
Principle #15Dynamics

2Speed

If volatile memory is used for cache operations, then access speed is improved, but data reliability during power failures deteriorates

Engineering Contradiction:
Improveaccess speedVSAvoiddata reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system prepares for potential power failures by implementing a power failure indicator mechanism that monitors the state of volatile memory. Before data is lost due to power loss, the system can detect the vulnerability and trigger appropriate responses, such as prioritizing flush operations or setting protective measures, thereby cushioning against the reliability issue.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The power failure indicator provides feedback about the state of volatile memory and potential data loss risks. This feedback mechanism allows the system to monitor when data in volatile memory is at risk and adjust operations accordingly, balancing the need for fast volatile memory access with the concern for data reliability during power failures.

Inventive Principle:
Principle #23Feedback

3Productivity

If data is stored in volatile memory for fast access, then productivity is improved, but loss of information increases during power failures

Engineering Contradiction:
Improvedata storage and retrieval efficiencyVSAvoiddata loss during power failures
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The system performs preliminary actions by implementing a power failure indicator that proactively identifies when data in volatile memory is vulnerable to loss. This early detection allows the system to take preventive measures before power failure occurs, such as prioritizing data flush operations or adjusting caching strategies, thereby reducing information loss while maintaining productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes operational parameters based on the power failure indicator state. When the indicator shows vulnerability, the system adjusts its behavior by modifying cache policies, prioritizing flush operations, or changing data placement strategies. This dynamic parameter adjustment allows the system to optimize between productivity and data protection based on current conditions.

Inventive Principle:
Principle #35Parameter changes

4Quantity of substance

If page swapping is implemented to optimize memory usage, then memory capacity utilization is improved, but access time increases

Engineering Contradiction:
Improvememory capacity utilizationVSAvoidaccess time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system implements page swapping selectively based on the power failure indicator and access patterns. Instead of swapping all pages, the system performs partial swapping of only those pages that are less critical or have lower access priority. This partial action approach maintains sufficient memory capacity utilization while minimizing the time penalty associated with swapping operations.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250013367A1Performance Optimization for Storing Data in Memory Services Configured on Storage Capacity of a Data Storage Device
Publication Date: 2025.01.09 MICRON TECHNOLOGY INC
  • US20250013367A1 patent drawing
  • US20250013367A1 patent drawing
  • US20250013367A1 patent drawing

AI summary

Techniques to improve performance of storing data to memory addresses implemented in a storage capacity of a memory sub-system. A connection from the memory sub-system to a host system supports both a protocol for cache-coherent memory access to a memory device implemented in the storage capacity and a protocol for storage access. The memory sub-system can use a cache memory to cache pages of the memory device for accessing over the connection. A storage access queue can be configured to provide a command configured to store data at a memory address in the memory device. Such commands can be entered in the queue when the cache memory is temporarily unavailable, or to cause the memory sub-system to swap a cached page from the cache memory to the storage capacity.