Memory Sub-System Data Migration via Tiered Cell Architecture

Solution Overview

Problem

Memory devices utilizing quad-level cells (QLCs) offer higher storage density but result in lower write performance and reduced cell life, along with increased wear-out conditions due to extreme temperatures, which existing memory sub-systems struggle to mitigate effectively.

Innovation Solution

Implementing a data migration component that writes data to a dynamic memory tier using single-level cells (SLCs), multi-level cells (MLCs), and triple-level cells (TLCs) and migrates it to a static memory tier using QLCs, thereby addressing the performance and reliability issues associated with QLCs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If quad-level cells (QLCs) are used to increase storage density, then storage density is improved, but write performance deteriorates and cell life is reduced

Engineering Contradiction:

Improvestorage densityVSAvoidwrite performance

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The memory device is segmented into multiple memory tiers (first memory tier with SLCs/MLCs/TLCs and second memory tier with QLCs). Each tier handles different workload characteristics, allowing the system to achieve both high storage density from QLCs and high write performance from SLCs/MLCs/TLCs through hierarchical data placement and migration.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If quad-level cells (QLCs) are used to increase storage density, then storage density is improved, but reliability deteriorates due to increased wear-out conditions from extreme temperatures

Engineering Contradiction:

Improvestorage densityVSAvoidcell life

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The memory device is segmented into multiple memory tiers (first memory tier with SLCs/MLCs/TLCs and second memory tier with QLCs). Each tier handles different workload characteristics, allowing the system to achieve both high storage density from QLCs and high write performance from SLCs/MLCs/TLCs through hierarchical data placement and migration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The controller acts as an intermediary that manages data migration between memory tiers based on temperature conditions and workload requirements. It monitors temperature thresholds and automatically migrates data between tiers to protect QLCs from extreme temperature wear while maintaining storage density.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If a dynamic memory tier with SLCs/MLCs/TLCs is used to improve write performance, then write performance is improved, but storage density decreases

Engineering Contradiction:

Improvewrite performanceVSAvoidstorage density

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The memory device is segmented into multiple memory tiers (first memory tier with SLCs/MLCs/TLCs and second memory tier with QLCs). Each tier handles different workload characteristics, allowing the system to achieve both high storage density from QLCs and high write performance from SLCs/MLCs/TLCs through hierarchical data placement and migration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs periodic data migration between memory tiers based on temperature conditions and workload patterns. This periodic action allows the dynamic tier to maintain high write performance while the static tier accumulates storage density, with data being redistributed as conditions change.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS11829650B2Memory sub-system data migration

Publication Date: 2023.11.28 MICRON TECHNOLOGY INC

AI summary

A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).