Memory Sub-System Ordered Error Recovery Schedule
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Solution Overview
Problem
Conventional memory devices with NAND-based storage media face challenges in accurately predicting, diagnosing, and addressing bit errors due to retention-related charge loss, endurance-related charge leakage, and other undesirable behaviors, often requiring multiple error recovery procedures that consume processing resources and are inefficient.
Innovation Solution
Implementing a memory sub-system with a single error recovery schedule that executes ordered error recovery operations to address multiple types of undesirable behaviors in a single iteration, reducing the need for diagnostic processes and conserving processing resources by executing error recovery operations in a predetermined order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple error recovery procedures are used to address different types of bit errors, then error recovery reliability is improved, but processing time and device complexity increase
Solution Approach 1:
The error recovery process is segmented into a single unified schedule that handles multiple error types (retention-related, endurance-related, and other undesirable behaviors) through a predetermined sequence of operations. This segmentation by type is consolidated into one integrated recovery procedure rather than multiple separate procedures, reducing processing time while maintaining comprehensive error coverage.
Solution Approach 2:
A single error recovery schedule is designed to perform multiple functions by addressing different error types through a unified process. The schedule incorporates ordered error recovery operations that can handle retention-related charge loss, endurance-related charge leakage, and other undesirable behaviors, making one procedure serve multiple purposes rather than requiring separate specialized procedures for each error type.
2Reliability
If multiple error recovery procedures are implemented for different error types, then error recovery comprehensiveness is improved, but device complexity increases
Solution Approach 1:
Multiple error recovery procedures that would traditionally be separate and distinct are merged into a single unified error recovery schedule. This schedule combines operations for addressing retention-related errors, endurance-related errors, and other undesirable behaviors into one integrated process, reducing the number of separate procedures while maintaining comprehensive error coverage.
Solution Approach 2:
The single error recovery schedule is designed with multi-functionality to handle various error types through a predetermined sequence of operations. By making one procedure serve multiple purposes (addressing different error types), the system achieves comprehensive error recovery without requiring multiple specialized procedures, thereby reducing overall device complexity.
3Measurement precision
If diagnostic processes are performed to determine error type before recovery, then error recovery precision is improved, but processing resources are consumed
Solution Approach 1:
The error recovery schedule is prepared in advance with a predetermined sequence of operations that does not require real-time diagnostic analysis to determine error type. The schedule is pre-configured to handle various error types in a specific order, eliminating the need for resource-intensive diagnostic processes before recovery begins. This preliminary preparation allows the system to proceed directly to recovery operations.
Data Source
AI summary
A memory system is disclosed, including a memory component and a processing device configured to decode one or more codewords saved to a memory region of the memory component, detect that a number of bit errors corresponding to the decoding of the codeword exceeds a correction capability of the processing device, and execute an error recovery routine to reduce the number of detected bit errors to within the correction capability. The error recovery routine can include error recovery operations that are sequentially executed either until the number of bit errors is successfully reduced to within the correction capability or until a set of the error recovery operations has been executed. The error recovery operations can be ordered according to one or more factors, including energy used to execute a respective error recovery operation, a duration of the respective operation, and/or a likelihood of success of the respective operation.