Memory Sub-System Programming Using Fewer Page Buffers

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Solution Overview

Problem

Conventional memory sub-systems require a large number of page buffers to program data to memory devices with multiple levels, leading to increased on-chip area and manufacturing costs, as the number of buffers needed scales with the number of bits capable of being stored.

Innovation Solution

A memory sub-system that programs data using fewer page buffers by providing charge level indicators to the memory device, allowing it to move memory cells to target charge levels in multiple programming steps, reducing the need for additional latches and optimizing the performance/cost ratio for mixed SLC, TLC, and QLC implementations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional memory sub-systems use a large number of page buffers to program data to memory devices with multiple levels, then the programming capability for multi-level cells is improved, but the on-chip area and manufacturing costs increase

Engineering Contradiction:

Improveprogramming capability for multi-level cellsVSAvoidon-chip area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent segments the programming process into multiple programming steps, where each step programs a portion of the data to the memory cells. Instead of requiring all page buffers to be available simultaneously, the system divides the data programming task across sequential steps, reducing the peak buffer requirement while maintaining full programming capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-charging bit lines and preparing programming voltage before actual data programming. This allows the system to optimize buffer usage by preparing certain operations in advance, reducing the simultaneous buffer requirements during critical programming operations.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

Engineering Contradiction:

Improveprogramming capability for multi-level cellsVSAvoidmanufacturing costs

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

By segmenting the programming process into multiple steps, the patent reduces the total number of page buffers required in the memory device. This reduction in buffer count directly lowers manufacturing complexity and cost, while the segmented approach maintains full programming capability through sequential operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic buffer allocation where page buffers are reused across different programming steps rather than being statically assigned. This dynamic approach allows fewer physical buffers to handle the programming of multi-level cells, reducing manufacturing requirements while maintaining adaptability.

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If additional latches are added to support QLC programming, then the programming capability is improved, but the on-chip area and device complexity increase

Engineering Contradiction:

Improveprogramming capability for QLCVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments QLC programming into multiple programming steps, each handling a portion of the 4-bit data. This segmentation allows the use of fewer latches per cell compared to conventional simultaneous programming approaches, reducing device complexity while maintaining full QLC programming capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system uses dynamic latch allocation where the same latches are reused across different programming steps for different data portions. This dynamic reuse reduces the total latch count required for QLC support, simplifying device architecture while maintaining programming versatility.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11869595B2Memory device programming technique using fewer latches

Publication Date: 2024.01.09 MICRON TECHNOLOGY INC

AI summary

A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.