Memory Sub-System Autonomous Proof of Space Testing

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Solution Overview

Problem

Conventional memory sub-systems face challenges in efficiently testing memory cells during manufacturing without consuming their useful life and require significant host system resources, which limits autonomous operation and energy efficiency in proof of space activities.

Innovation Solution

The use of proof of space lookup tables stored in memory sub-systems allows for autonomous testing and operation, reducing the need for host system assistance and energy consumption, with internal hosts managing proof of space activities independently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional memory testing methods are used during manufacturing, then memory cells can be tested, but the useful life of the memory cells is consumed

Engineering Contradiction:
Improvememory cell testing capabilityVSAvoiduseful life of memory cells
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent applies preliminary action by performing memory cell testing during the manufacturing process before the memory sub-system is deployed for normal operation. This ensures that testing occurs while the memory cells are still in their initial state, maximizing their remaining useful life for actual data storage operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If host system resources are used for proof of space activities, then testing can be performed, but host system resources are significantly consumed

Engineering Contradiction:
Improveproof of space testing capabilityVSAvoidhost system energy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements self-service by enabling the memory sub-system to autonomously perform proof of space testing activities using its own internal resources. The memory sub-system generates and validates proof of space responses independently without requiring significant host system intervention, thereby reducing host system energy consumption and resource utilization.

Inventive Principle:
Principle #25Self-service

3Reliability

If host system assistance is required for memory testing, then testing can be performed, but autonomous operation is limited

Engineering Contradiction:
Improvememory testing capabilityVSAvoidautonomous operation capability
Core Design Contradiction:
ReliabilityVSExtent of automation

Solution Approach 1:

The patent enables autonomous operation by implementing self-service capabilities within the memory sub-system. The system can independently generate proof of space challenges, retrieve stored data, validate responses, and perform testing without requiring host system assistance, thereby maximizing the extent of automation and independent operation.

Inventive Principle:
Principle #25Self-service

4Extent of automation

If proof of space lookup tables are stored in memory sub-systems, then autonomous operation is enabled, but memory capacity is utilized

Engineering Contradiction:
Improveautonomous proof of space operationVSAvoidmemory capacity
Core Design Contradiction:
Extent of automationVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by pre-storing proof of space lookup tables in the memory sub-system during manufacturing. This preliminary preparation enables the system to autonomously generate and validate proof of space responses without requiring external assistance during operation, trading some memory capacity for significant gains in autonomous operation capability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240220132A1Test Memory Sub-Systems through Validation of Responses to Proof of Space Challenges
Publication Date: 2024.07.04 MICRON TECHNOLOGY INC
  • US20240220132A1 patent drawing
  • US20240220132A1 patent drawing
  • US20240220132A1 patent drawing

AI summary

A memory sub-system, such as a solid-state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.