Memory Sub-System Write Sequence Tracking
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Solution Overview
Problem
The existing memory sub-systems face challenges in managing address mapping tables efficiently, particularly in autonomous vehicles and IoT devices, where the total bytes written (TBW) exceed user capacity, leading to substantial resource exhaustion and difficulty in tracking sequential data writes for snapshot retrieval.
Innovation Solution
A memory sub-system that tracks the sequence of logical addresses written with data without repeatedly updating the logical to physical (L2P) address mapping table, using a linked list to identify data storage locations and sequences, allowing for efficient retrieval of snapshots without maintaining extensive address mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the L2P address mapping table is repeatedly updated to track sequential data writes, then the accuracy of snapshot retrieval is improved, but the resource consumption and TBW increase substantially
Solution Approach 1:
The patent divides the address mapping tracking function into two separate components: (1) a write sequence tracker that maintains a lightweight linked list of logical addresses in write order, and (2) a traditional L2P table that maps logical addresses to physical locations. This segmentation allows the system to track write sequences without repeatedly updating the entire L2P table, thereby reducing resource consumption while maintaining snapshot retrieval accuracy.
Solution Approach 2:
The patent introduces a write sequence tracker as an intermediary data structure between the host system and the L2P table. This tracker maintains a linked list of logical addresses in write order, serving as a mediator that enables snapshot retrieval without requiring frequent updates to the L2P table. The intermediary absorbs the overhead of sequence tracking, preventing it from propagating to the resource-intensive L2P table updates.
2Reliability
If the L2P address mapping table is maintained to ensure accurate data location tracking, then the reliability of data retrieval is improved, but the device complexity increases
Solution Approach 1:
The patent segments the address mapping management into two independent structures: a write sequence tracker that maintains write order information, and a traditional L2P table that maintains address translations. This segmentation reduces device complexity by separating the sequence tracking function from the address mapping function, allowing each component to be optimized independently while maintaining overall reliability.
Solution Approach 2:
The patent creates a simplified copy of the address mapping information in the form of a linked list within the write sequence tracker. This copy contains only the essential write sequence information without the full overhead of the L2P table structure. The linked list copy enables reliable snapshot retrieval by providing a lightweight alternative to maintaining the complete L2P table for sequence tracking purposes.
3Productivity
If extensive address mapping tables are maintained to support high throughput writes, then the productivity of data storage is improved, but the loss of substance increases due to frequent updates
Solution Approach 1:
The patent extracts the write sequence tracking function from the L2P table update process. By maintaining a separate write sequence tracker with a linked list structure, the system can track write sequences without triggering L2P table updates. This extraction eliminates the harmful side effect of frequent L2P updates while preserving the high throughput capability needed for productivity.
Solution Approach 2:
The patent enables continuous high-speed data writing by decoupling the write operation from the address mapping update operation. The write sequence tracker continuously records logical addresses in write order without requiring synchronous updates to the L2P table. This continuity allows the storage system to maintain high productivity while minimizing the TBW associated with address mapping maintenance.
Data Source
AI summary
A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.