Memory Architecture Isolating Sub-Wordline Defects for ECC Recovery
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Solution Overview
Problem
Traditional memory architectures, especially in stacked memory solutions, face challenges in error correction due to the risk of multiple bits being affected by a single defective sub-wordline, making it difficult to recover corrupted data effectively with existing ECC mechanisms.
Innovation Solution
The improved memory chip architecture isolates potential error-inducing manufactured structures to only a few I/O lines, containing errors within a single output bit and facilitating easier ECC recovery, by connecting a defect-prone structure to minimal I/O bits, reducing the impact of errors on other bits in a read word.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional memory architectures are used with stacked memory solutions, then manufacturing complexity is reduced, but error recovery capability deteriorates due to multiple bits being affected by a single defective sub-wordline
Solution Approach 1:
The patent segments the memory chip's I/O lines into multiple groups, where each group is connected to a different sub-wordline. This segmentation ensures that a defect in one sub-wordline affects only a limited number of I/O lines within its group, rather than all I/O lines. This allows ECC mechanisms to successfully recover from errors by isolating them to manageable segments.
Solution Approach 2:
The patent implements local quality by creating non-uniform connections between sub-wordlines and I/O lines. Specifically, each I/O line group is selectively connected to specific sub-wordlines based on their error susceptibility characteristics. This localized optimization ensures that defect-prone sub-wordlines are connected to fewer I/O lines, reducing the impact of potential errors in those specific regions.
2Ease of manufacture
If defective sub-wordlines are connected to multiple I/O lines, then manufacturing simplicity is maintained, but data integrity deteriorates due to error spread across multiple bits
Solution Approach 1:
The patent divides the I/O lines into multiple segments or groups, where each group is connected to a limited subset of sub-wordlines. This segmentation prevents error propagation across all I/O lines when a sub-wordline defect occurs, as the defect is confined to only those I/O lines connected to the defective sub-wordline within its segment.
Solution Approach 2:
The patent applies different connection strategies to different I/O line groups based on local error susceptibility. I/O lines connected to defect-prone sub-wordlines are grouped separately and limited in number, while I/O lines connected to reliable sub-wordlines can be grouped more freely. This localized differentiation maintains manufacturing feasibility while improving data integrity.
3Device complexity
If error-inducing structures are connected to many I/O lines, then device complexity is reduced, but ECC recovery effectiveness deteriorates due to multiple corrupted bits
Solution Approach 1:
The patent segments the connection structure between sub-wordlines and I/O lines into multiple independent groups. Each group contains a limited number of I/O lines connected to specific sub-wordlines, ensuring that errors are contained within small segments. This segmentation maintains relatively simple connection structures while dramatically improving ECC recovery effectiveness by limiting error spread.
Solution Approach 2:
The patent deliberately limits the number of I/O lines connected to each sub-wordline group to a minimal necessary amount, rather than providing comprehensive coverage. This partial connection strategy ensures that even if a sub-wordline is defective, the number of corrupted bits remains within the correction capability of ECC mechanisms, sacrificing some potential performance for reliability.
Data Source
AI summary
A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.