Memory Subarray Remapping for Defective Bit Line Repair
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in rescuing defective bit lines when the number of defective bit lines exceeds the number of spare bit lines, particularly as miniaturization increases, leading to higher occurrence probabilities of bad columns, increased costs, and resource constraints.
Innovation Solution
A semiconductor memory device with a memory cell array comprising first and second subarrays, where a control circuit activates corresponding word lines in both subarrays to access memory cells in the second subarray when the number of defective bit lines in the first subarray exceeds the number of spare bit lines, allowing for efficient rescue of defective bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more spare bit lines are provided to maintain the same repair rate as miniaturization progresses, then the repair capability is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes bit lines from different subarrays serve multiple functions. Specifically, bit lines in a first subarray can be used not only for accessing memory cells in that subarray but also for replacing defective bit lines in other subarrays. This multi-functional usage allows the system to handle more defects without adding more spare bit lines, thereby maintaining repair rate while reducing device complexity
Solution Approach 2:
The patent combines the spare bit line resources from multiple subarrays into a shared pool. Instead of having dedicated spare bit lines in each subarray, the system merges these resources and allows any subarray to utilize spare bit lines from other subarrays when defects occur. This consolidation reduces the total number of spare bit lines needed while maintaining the same repair capability
2Reliability
If the number of defective bit lines in a subarray exceeds the number of spare bit lines in that subarray, then the conventional repair method fails, but the patent enables successful repair by accessing memory cells in other subarrays
Solution Approach 1:
The patent extends the repair capability from a single-subarray dimension to a multi-subarray dimension. Instead of limiting defect repair within the same subarray where the defective bit line is located, the system allows replacement of defective bit lines in one subarray using bit lines from other subarrays. This cross-subarray approach adds a new dimension to the repair process, enabling successful repair even when local spare bit lines are insufficient
Solution Approach 2:
The patent creates a copying mechanism where memory cells in one subarray can serve as replacements for memory cells in another subarray. When a bit line in subarray A is defective, the system can access and use the corresponding memory cells in subarray B as substitutes, effectively copying the functional role across subarrays. This copying approach enables repair capability to exceed the limits of local spare bit lines
Data Source
AI summary
A semiconductor memory device and control method thereof are provided, repairing defective bit lines even if the number of defective bit lines exceeds that of a spare bit line in any subarray in multiple subarrays. The semiconductor memory device includes a memory cell array having multiple subarrays, and a controller, configured to activate the word line and a corresponding word line in a second subarray which is separately arranged from the first subarray in a column direction when activating any word line in a first subarray of the plurality of subarrays. The controller is further configured to access the memory cells connected to the activated word line in the second subarray instead of the memory cells connected to the activated word line in the first subarray when a first condition (i.e., the number of defective bit lines exceeds the number of spare bit lines in the first subarray) is met.