Dynamic Power Saving Memory Architecture Sub-Array Segmentation
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Solution Overview
Problem
Current memory architectures in hand-held devices face challenges in reducing dynamic power consumption, which is a significant concern due to the long bit lines resulting in high capacitance and increased power usage, while minimizing performance reductions.
Innovation Solution
The memory architecture is modified by dividing it into sub-arrays with all bit lines and a portion of the word lines, using multiplexers to select the appropriate sub-array based on the memory address, thereby shortening bit lines and reducing capacitance, thus lowering dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory is divided into sub-arrays with all bit lines and a portion of word lines, then the bit line length is reduced and capacitance is lowered, but the device complexity increases due to the need for multiplexers and decoder modifications
Solution Approach 1:
The memory array is segmented into multiple sub-arrays, where each sub-array contains all bit lines but only a portion of the word lines. This segmentation reduces the length of bit lines in each sub-array, thereby reducing capacitance and dynamic power consumption. The word lines are distributed across multiple sub-arrays, and multiplexers are used to select which sub-array is currently active, allowing the system to maintain full memory functionality while reducing power consumption through shorter bit line segments.
2Use of energy by moving object
If bit lines are shortened to reduce capacitance and dynamic power, then power consumption is reduced, but the memory capacity and density per unit area decrease
Solution Approach 1:
The memory architecture transitions from a two-dimensional layout to a three-dimensional structure by stacking multiple sub-arrays vertically. Each sub-array contains all bit lines but a portion of word lines, and multiple sub-arrays are stacked to achieve the total memory capacity. This vertical stacking allows the system to maintain short bit lines (reducing capacitance and power) while achieving high memory density through the additional vertical dimension.
Solution Approach 2:
Each sub-array contains a complete set of bit lines that can serve multiple functions across different sub-arrays. The bit lines in each sub-array are universal in that they can access memory cells in their respective sub-array, and through the multiplexer system, the same bit line structure is replicated across multiple sub-arrays to provide full memory access capability without requiring proportionally longer bit lines.
Data Source
AI summary
A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and configured to control each of the word lines. The memory also includes multiplexers coupled to each of the interface ports. The multiplexers are configured to cause the selection of one of the sub-arrays based upon an address of a memory cell received at one or more of the interface ports.