Memory Subarray Segmentation for Cache Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current processing-in-memory (PIM) systems face inefficiencies due to high power consumption and performance limitations from external data transfer and mismatched pitch rules between processing resources and memory arrays, leading to suboptimal memory access times and density.
Innovation Solution
A memory device architecture with subarrays having shorter and longer digit lines, where shorter digit line subarrays are used as caches for faster access and computation, and longer digit line subarrays for storage, with a cache controller managing data movement between them, and sensing circuitry formed on pitch with memory cells to perform operations locally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If data is transferred externally between processing resources and memory arrays, then processing can be performed, but power consumption increases and access time worsens
Solution Approach 1:
The memory device is segmented into multiple subarrays with different digit line lengths. Shorter digit line subarrays are used for frequently accessed data (cache), while longer digit line subarrays store less frequently accessed data. This segmentation allows data to be kept closer to processing resources when needed, reducing access time and power consumption for frequent operations while maintaining storage capacity.
Solution Approach 2:
The patent introduces a spatial dimension to data storage by varying digit line lengths across different subarrays. Instead of uniform storage, data is distributed across subarrays positioned at different distances from processing resources, creating a hierarchical storage structure within the same memory device that optimizes both speed and energy efficiency.
2Speed
If shorter digit line subarrays are used for cache, then access speed improves, but device complexity increases
Solution Approach 1:
The memory device uses a unified architecture where all subarrays can function as either cache or storage depending on the operation. The same sensing circuitry and data movement mechanisms serve both shorter and longer digit line subarrays, allowing the system to dynamically allocate functions without requiring separate specialized structures for cache and storage.
Solution Approach 2:
The memory device performs data movement and processing operations autonomously within its structure. The sensing circuitry can directly move data between subarrays and perform computations without requiring external intervention, allowing the shorter digit line subarrays to serve as self-sufficient cache that reduces the need for complex external control mechanisms.
3Productivity
If sensing circuitry is formed on pitch with memory cells, then local processing efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The sensing circuitry is integrated at specific locations within the memory device structure, formed on pitch with memory cells in shorter digit line subarrays. This local integration provides processing efficiency where needed most (in the cache region) without requiring uniform high-precision integration across the entire device, thereby managing manufacturing complexity while maximizing performance benefits.
Data Source
AI summary
The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.