Memory Subarray Segmentation for Row Cycle Time Reduction
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Solution Overview
Problem
In dynamic random-access memory (DRAM), the row cycle time is prolonged due to the need for precharging digit lines before subsequent memory access, which can be exacerbated by the requirement for additional array circuitry that reduces memory storage area and increases power consumption.
Innovation Solution
A controller circuit that manages multiple subarrays within a memory bank, allowing for contemporaneous access to one subarray while precharging another, by utilizing address restrictions to minimize row cycle time through shared or separate precharge circuits and sense amplifiers, thereby optimizing row cycle time based on access patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If additional array circuitry is added to reduce row precharge time, then row cycle time is reduced, but memory storage area is reduced and power consumption is increased
Solution Approach 1:
The memory array is divided into multiple subarrays (first subarray, second subarray, third subarray) that can be accessed independently. This segmentation allows the controller to perform precharge operations on one subarray while simultaneously accessing another subarray, thereby reducing the row cycle time without adding additional array circuitry. The segmentation principle resolves the contradiction by enabling time-parallel operations that effectively reduce the perceived row cycle time while maintaining the original memory area.
Solution Approach 2:
The controller performs precharge operations on a first subarray before the row cycle time expires, allowing subsequent memory accesses to proceed without waiting for the precharge to complete. This preliminary action of initiating precharge early and overlapping it with other memory operations reduces the effective row cycle time without requiring additional circuitry to accelerate the precharge process itself.
2Loss of time
If additional array circuitry is added to reduce row precharge time, then row cycle time is reduced, but power consumption is increased
Solution Approach 1:
By segmenting the memory array into multiple subarrays with independent access paths, the system can perform precharge operations on one subarray while simultaneously conducting memory accesses on other subarrays. This eliminates the need for additional array circuitry that would consume extra power, as the existing circuitry is reused in a time-parallel manner across different subarrays.
Solution Approach 2:
The controller initiates precharge operations on a first subarray before the current row cycle time expires, allowing the precharge to complete in the background during subsequent memory accesses to other subarrays. This preliminary initiation of precharge avoids the need for faster (and more power-consuming) precharge circuitry by instead using time-parallel processing to achieve the same timing effect.
3Speed
If row precharge time is reduced by adding array circuitry, then memory access speed is improved, but device complexity is increased
Solution Approach 1:
The memory array is segmented into multiple subarrays that can be accessed independently through separate word lines and digit lines. This segmentation enables the controller to overlap precharge operations on one subarray with memory accesses on other subarrays, improving memory access speed without adding complex additional array circuitry. The existing circuitry is simply organized into multiple independent access paths.
Solution Approach 2:
The controller performs preliminary precharge actions on a first subarray before the row cycle time expires, allowing subsequent memory accesses to proceed in parallel without waiting for precharge completion. This preliminary action improves memory access speed by eliminating the sequential dependency between precharge and access operations, while avoiding the need for additional array circuitry that would increase device complexity.
Data Source
AI summary
Methods and apparatuses are disclosed including an apparatus that includes a controller circuit configured to access a first subarray of a memory and to access a second subarray of the memory subsequent to accessing the first subarray but contemporaneous with precharging a portion of the first subarray by a precharge circuit associated with the first subarray.