Memory Sub-block Compensation for Drift Errors
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Solution Overview
Problem
Computation circuits in memory experience errors due to manufacturing process parameter drift, temperature changes, voltage variations, and memory cell deterioration, leading to inaccurate computation results and reduced efficiency.
Innovation Solution
A memory apparatus comprising a memory sub-block, a reference memory sub-block, and a control circuit, where the reference memory sub-block is pre-programmed with a reference weight value to generate a reference computation value, and an adjustment value is calculated to correct the computation result generated by the memory sub-block, thereby improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a computation circuit in memory is used to perform multiply-accumulate operations, then the circuit area is reduced and computation efficiency is improved, but manufacturing process parameter drift, temperature changes, and voltage changes cause memory cell current drift leading to computation result errors
Solution Approach 1:
The patent applies preliminary action by introducing a calibration phase before the computation phase. During the calibration phase, reference computation values are obtained by applying reference input signals to the memory sub-block, and adjustment values are calculated based on the difference between reference computation values and expected values. These adjustment values are stored and subsequently applied to correct computation results during the actual computation phase, thereby compensating for drift errors before they affect computation accuracy.
Solution Approach 2:
The patent implements feedback by using the computation results (or reference computation values) to generate adjustment values that are then fed back to correct subsequent computation results. The control circuit continuously monitors the computation output and dynamically adjusts the computation results by adding adjustment values, creating a closed-loop feedback system that compensates for manufacturing drift, temperature changes, and voltage variations in real-time.
2Device complexity
If memory cells are used for computation operations, then the device complexity is reduced, but manufacturing process parameter drift and memory cell deterioration cause current distribution offset reducing computation accuracy
Solution Approach 1:
The patent applies self-service by enabling the memory sub-block to perform dual functions: it serves both as the computation engine for multiply-accumulate operations and as its own calibration reference through the introduction of reference input signals. The same memory cells that perform computation also generate reference computation values during calibration, allowing the system to self-diagnose and self-correct for manufacturing drift without requiring separate reference circuits or additional complex calibration hardware.
3Device complexity
If no compensation mechanism is implemented, then the device complexity remains low, but temperature changes and voltage changes cause memory cell electrical changes leading to incorrect computation results
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting computation results based on environmental conditions. The system changes the computational parameters (adding adjustment values) based on detected variations in temperature, voltage, and manufacturing drift. The adjustment values themselves are parameters that are calculated during calibration and applied during computation to compensate for environmental factors, effectively transforming the system's response to environmental changes from passive to active compensation.
Data Source
AI summary
A memory apparatus and compensation method for a computation result thereof are provided. The memory apparatus includes a memory sub-block, a reference memory sub-block and a control circuit. During a computation phase, the memory sub-block receives an input signal, and generates a computation result by a multiply-accumulate operation according to the input signal. The reference memory sub-block includes a plurality of memory cells pre-programmed with a reference weight value. The reference memory sub-block receives a reference input signal during a calibration phase, and generates a reference computation value by a multiply-accumulate operation according to the reference input signal and the reference weight value. The control circuit generates an adjustment value according to the reference computation value and a standard computation value, and during the computation phase, adjusts the computation result according to the adjustment value to generate an adjusted computation result.