Non-Volatile Memory Sub-Block Erase Control for Disturb Reliability

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Solution Overview

Problem

Conventional block-unit control techniques struggle to provide adequate performance as memory blocks increase in size, leading to reliability issues due to disturb deterioration caused by adjacent sub-block operations in non-volatile memory devices.

Innovation Solution

A non-volatile memory device with first and second sub-blocks, each selectable as a unit of an erase operation, and control logic to calculate on-cell and off-cell counts, generate disturb information, and adjust operating conditions based on this information to improve performance and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory blocks are increased in size to improve storage capacity, then storage capacity is improved, but reliability deteriorates due to disturb deterioration caused by adjacent sub-block operations

Engineering Contradiction:
Improvestorage capacityVSAvoidreliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) that can be independently operated. This segmentation allows selective erasure of only the required sub-block while protecting adjacent sub-blocks from disturb deterioration, thereby maintaining reliability while supporting large storage capacity through increased block size.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If conventional block-unit control techniques are used for larger memory blocks, then storage capacity is improved, but performance deteriorates due to inadequate control for increased block capacity

Engineering Contradiction:
Improveblock capacityVSAvoidperformance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) that can be independently operated. This segmentation allows selective erasure of only the required sub-block while protecting adjacent sub-blocks from disturb deterioration, thereby maintaining reliability while supporting large storage capacity through increased block size.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control logic dynamically determines which sub-blocks require erasure based on actual data storage needs, rather than erasing entire blocks statically. This dynamic control optimizes performance by minimizing unnecessary erase operations while maintaining adequate control for increased block capacity.

Inventive Principle:
Principle #15Dynamics

3Productivity

If adjacent sub-block operations are performed, then storage operations are improved, but reliability deteriorates due to disturb deterioration

Engineering Contradiction:
Improvestorage operationsVSAvoidreliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Before performing erase operations on a target sub-block, the control logic identifies and protects adjacent sub-blocks by excluding them from the erase operation. This preliminary protective action prevents disturb deterioration in adjacent sub-blocks, maintaining reliability while enabling efficient storage operations on the target sub-block.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The memory block is divided into multiple sub-blocks (first sub-block and second sub-block) that can be independently operated. This segmentation allows selective erasure of only the required sub-block while protecting adjacent sub-blocks from disturb deterioration, thereby maintaining reliability while supporting large storage capacity through increased block size.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250298517A1Non-volatile memory device, a storage device including the non-volatile memory device and a method of operating the storage device
Publication Date: 2025.09.25 SAMSUNG ELECTRONICS CO LTD
  • US20250298517A1 patent drawing
  • US20250298517A1 patent drawing
  • US20250298517A1 patent drawing

AI summary

Provided are a non-volatile memory device, a storage device including the non-volatile memory device, and a method of operating the storage device. The non-volatile memory device includes a memory cell array including first and second sub-blocks that are respectively formed from first and second portions of memory cell strings that extend through a plurality of wordlines stacked on a substrate, the first and second sub-blocks each being selectable as a unit of an erase operation; and control logic configured to calculate an off-cell count based on a first voltage for a plurality of memory cells in the first sub-block, calculate an on-cell count based on a second voltage for the plurality of memory cells, and control an operation for the first sub-block to be performed based on an operating condition corresponding to disturb information generated by the off-cell count and the on-cell count.