Memory Sub-Block Erase Control via Dummy Word Lines
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Solution Overview
Problem
Existing memory devices face inefficiencies and reliability issues during erase operations, particularly when increasing the number of cell strings in memory blocks, leading to prolonged erase times and degraded memory efficiency.
Innovation Solution
The memory device is divided into sub-blocks, with a control circuit managing independent erase operations by applying different transfer voltages to selected and unselected sub-blocks, using dummy word lines to prevent interference and optimize erase voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of cell strings in memory blocks is increased, then storage capacity is improved, but erase operation time is prolonged and memory efficiency is degraded
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block), each with its own set of word lines. This segmentation allows independent erase operations on each sub-block, enabling parallel processing and reducing overall erase time while maintaining high storage capacity through increased cell string density.
2Quantity of substance
If the number of cell strings in memory blocks is increased, then storage capacity is improved, but erase operation time is prolonged
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block), each with its own set of word lines. This segmentation allows independent erase operations on each sub-block, enabling parallel processing and reducing overall erase time while maintaining high storage capacity through increased cell string density.
Solution Approach 2:
The invention applies erase operations to only the necessary sub-blocks rather than the entire memory block. By performing partial erase operations on selected sub-blocks independently, the system reduces unnecessary erase time while maintaining the ability to expand storage capacity through additional cell strings.
3Reliability
If dummy word lines are added to separate sub-blocks, then erase operation reliability is improved, but device complexity increases
Solution Approach 1:
Dummy word lines are extracted and placed between the first and second sub-blocks to prevent interference during erase operations. These dedicated dummy word lines isolate voltage effects between sub-blocks, improving erase reliability through electrical separation while adding minimal structural complexity compared to the overall memory device architecture.
Data Source
AI summary
A memory device including: a memory block including a word lines, word lines located in the middle of the word lines are used as dummy word lines, a control circuit establish word lines stacked on one side and other side of the dummy word lines into a first and second sub-blocks, respectively, performs an independent erase operation on one of the first and second sub-blocks in an erase operation period, and a control logic differently sets a level of a first transfer voltage for controlling transfer of an erase common voltage to the selected sub-block and the level of a second transfer voltage for controlling transfer of the erase common voltage to the unselected sub-block, applies an erase allowable voltage from the erase common voltage to a word line of the selected sub-block, and floats a word line of the unselected sub-block, in the erase operation period.