3D Nonvolatile Memory Sub-Block Erase Management
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Solution Overview
Problem
The increasing storage capacity of semiconductor memory devices due to three-dimensional memory cell stacking causes issues with conventional memory management policies, leading to inefficiencies in erase operations and data reliability.
Innovation Solution
A nonvolatile memory device with sub-block management, where memory blocks are divided into smaller sub-blocks that can be erased independently, using a row decoder and voltage generator to apply specific voltages to word lines, minimizing interference between sub-blocks and ensuring data reliability through adaptive compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell stacking is used to increase storage capacity, then storage capacity is improved, but conventional memory management policies become inefficient and erase operations become problematic
Solution Approach 1:
The patent divides the memory block into multiple sub-blocks that can be erased independently. Each sub-block is defined by specific word line ranges, allowing selective erase operations without affecting the entire block. This segmentation enables efficient erase operations in high-capacity three-dimensional memory structures by processing only the necessary portions.
Solution Approach 2:
The patent applies different voltage levels to different regions of the memory block during erase operations. Specifically, a first voltage is applied to word lines within the target sub-block while a second voltage is applied to word lines outside the sub-block. This local differentiation ensures efficient erase of the selected sub-block while protecting other regions.
2Speed
If sub-block erase operations are performed, then erase operation speed is improved, but interference with unselected sub-blocks may occur
Solution Approach 1:
The patent applies different voltage levels to different regions of the memory block during erase operations. Specifically, a first voltage is applied to word lines within the target sub-block while a second voltage is applied to word lines outside the sub-block. This local differentiation ensures efficient erase of the selected sub-block while protecting other regions.
Solution Approach 2:
The patent applies a cut-off voltage to word lines adjacent to the selected sub-block before and during the erase operation. This preliminary protective action prevents high voltage from leaking into unselected sub-blocks, thereby avoiding interference and potential data corruption in adjacent regions.
3Reliability
If conventional block erase operations are used, then data reliability is maintained, but performance deteriorates due to dummy word lines and page copies
Solution Approach 1:
The patent divides the memory block into multiple sub-blocks that can be erased independently. Each sub-block is defined by specific word line ranges, allowing selective erase operations without affecting the entire block. This segmentation enables efficient erase operations in high-capacity three-dimensional memory structures by processing only the necessary portions.
Solution Approach 2:
The patent changes the voltage parameters applied during erase operations based on the specific sub-block being erased. Different voltage levels are applied to different word line regions, and cut-off voltages are dynamically adjusted to prevent interference. This adaptive parameter adjustment maintains data reliability while improving performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed erase operations without the need for dummy word lines or page copy, improving data reliability and reducing the number of merge operations, thus enhancing overall performance.
Implementation Method 1
providing at least one word line of the selected sub-block with a cut-off voltage for blocking interference with an unselected sub-block
Data Source
AI summary
A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.