Semiconductor Memory Sub-Block Erasure Voltage Control
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Solution Overview
Problem
Semiconductor memory devices face limitations in selecting and erasing target sub-blocks due to program sequence constraints, which restrict data reprogramming and increase the risk of program disturb and erase threshold voltage variations.
Innovation Solution
A semiconductor memory device and method that allow arbitrary selection of sub-blocks for erasure, with the control logic determining an erase verify voltage based on the position or program state of adjacent sub-blocks, enabling flexible erasure operations without sequence constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If sub-blocks are erased in sequence based on program order, then program disturb risk is reduced, but erasure flexibility is limited and data reprogramming efficiency decreases
Solution Approach 1:
The patent applies local quality by determining different erase verify voltages for different sub-blocks based on their specific positions and program states. Each sub-block receives a tailored erase verify voltage rather than a uniform voltage, allowing flexible erasure of any sub-block while maintaining reliability by adapting the voltage to local conditions.
2Productivity
If arbitrary sub-blocks can be selected for erasure, then data reprogramming flexibility improves, but threshold voltage variations increase
Solution Approach 1:
The patent changes the parameter of erase verify voltage based on the position and program state of the target sub-block. By adjusting this voltage parameter dynamically, the system enables arbitrary sub-block selection for erasure while compensating for threshold voltage variations through adaptive voltage selection.
3Measurement precision
If erase verify voltage is determined based on sub-block position, then erasure accuracy improves, but control complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing the relationship between sub-block positions and their corresponding erase verify voltages. The control logic is designed in advance to automatically determine the appropriate voltage based on position, simplifying the control process while maintaining high erase verify accuracy.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a read/write circuit and a control logic. The memory cell array includes a plurality of memory cells. The read/write circuit is configured to write data to the memory cell array or read data from the memory cell array. The control logic is configured to control the read/write circuit to perform a read/write operation for the memory cell array. The memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of sub-blocks. During an operation of erasing a sub-block in a memory block, the control logic selects a sub-block to be erased regardless of a sequence in which the sub-blocks have been programmed, and determines an erase verify voltage based on a position of the selected sub-block.