Multi-Tier Memory Sub-Block Programming for Er-to-A Failure Control
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in efficiently programming and boosting potential in multi-tier sub-blocks, leading to issues such as Er-to-A (erase to program) failures, particularly in three-tier and higher tiered structures like SLC, MLC, TLC, and QLC.
Innovation Solution
Implementing a multi-sub-block precharge scheme that applies a precharge spike on physical source side wordlines and ensures that the threshold voltage (Vth) of each sub-block follows a reverse order programming sequence, with '1' Vth in one sub-block not being lower than '0' Vth in the previous sub-block, thereby ensuring sufficient boosting for all sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If normal order programming sequence is used on upper sub-block, then programming efficiency is improved, but Er-to-A failures increase
Solution Approach 1:
The patent applies reverse order programming sequence to the lower sub-block and middle sub-block instead of the conventional normal order sequence. This inversion of the programming direction resolves the technical contradiction by preventing Er-to-A failures while maintaining programming efficiency through the multi-sub-block parallel architecture.
2Quantity of substance
If multi-tier sub-block structure is implemented, then memory capacity is increased, but programming complexity increases
Solution Approach 1:
The patent divides the memory block into multiple sub-blocks (upper, lower, and middle sub-blocks) that can be programmed independently with different programming sequences. This segmentation allows the system to manage complex multi-tier structures by breaking them into manageable units, each with optimized programming characteristics.
Solution Approach 2:
Different programming sequences are applied to different sub-blocks based on their specific characteristics. The upper sub-block uses normal order programming while the lower and middle sub-blocks use reverse order programming, optimizing each region's performance and reducing overall programming complexity.
3Reliability
If reverse order programming sequence is applied to lower and middle sub-blocks, then Er-to-A failures are reduced, but control complexity increases
Solution Approach 1:
The control circuitry dynamically selects different programming sequences for different sub-blocks based on their position and characteristics. This dynamic control approach reduces Er-to-A failures by adapting the programming sequence to each sub-block's specific requirements while managing control complexity through systematic decision-making.
Data Source
AI summary
A storage device is disclosed herein. The storage device comprises a non-volatile memory, where the non-volatile memory includes a block of 3N wordlines partitioned into a plurality of sub-blocks. The plurality of sub-blocks include an upper sub-block of a first subset of the block of 3N wordlines, a lower sub-block of a second subset of the block of 3N wordlines, and a middle sub-block of a third subset of the block of 3N wordlines. Further, the storage device comprises control circuitry coupled to the block of 3N wordlines and configured to: perform a program operation in a normal order programming sequence on the upper sub-block; perform a program operation in a reverse order programming sequence on the lower sub-block; and perform a program operation in the reverse order programming sequence on the middle sub-block.