Memory Device Sub-Block Segmentation for Read Efficiency
Solution Overview
Problem
Current memory devices face challenges in optimizing read operation efficiency due to the structural differences between three-dimensional and two-dimensional memory devices, leading to suboptimal performance in data retrieval processes.
Innovation Solution
The memory device incorporates a first and second sub-block with select transistors and memory cells, coupled through word lines, where the control logic manages voltage levels in stepwise increments to enhance read operation efficiency by turning on and off select transistors, thereby optimizing data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If voltage is applied to all word lines simultaneously in a three-dimensional memory device, then all memory cells can be accessed, but read operation efficiency deteriorates due to interference between adjacent sub-blocks
Solution Approach 1:
The memory device is divided into first and second sub-blocks with separate select transistor groups. The control logic selectively activates only the required sub-block during read operations, segmenting the memory access paths to prevent interference between adjacent sub-blocks while maintaining reliable data retrieval.
Solution Approach 2:
The control logic pre-charges bit lines and pre-phases word lines before actual read operations. This preliminary action prepares the circuit in advance, reducing access time and improving read operation efficiency without compromising data accuracy.
2Adaptability or versatility
If all select transistors are kept on to access any memory cell, then access flexibility is improved, but power consumption increases due to continuous current flow
Solution Approach 1:
The control logic dynamically controls the state of select transistors based on the specific read operation requirements. Only the select transistors corresponding to the active sub-block are turned on, while others remain off, providing flexible access to any memory cell while minimizing power consumption by avoiding continuous current flow through all select transistors.
3Speed
If voltage levels are increased rapidly to improve read speed, then data retrieval speed is improved, but voltage interference between sub-blocks increases causing read errors
Solution Approach 1:
By segmenting the memory into separate sub-blocks with independent select transistor control, high voltage levels can be applied to the active sub-block for fast reading without causing voltage interference in adjacent sub-blocks, thus achieving high speed data retrieval while preventing read errors.
Solution Approach 2:
The control logic acts as an intermediary that manages voltage distribution across different sub-blocks. It applies appropriate voltage levels to selected word lines and sub-blocks while keeping other sub-blocks at safe voltage levels, preventing voltage interference while enabling fast read operations in the active sub-block.
Data Source
AI summary
A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.